Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: VhdlCohen@aol.com
Date: Wed Dec 12 2001 - 08:12:52 PST
You are correct about not currently being synthesizable. But this style is
equivalent to the VHDL proposal to have implicit FSMs, where at each clock,
the FSM enters a new state.
Ben
In a message dated 12/12/01 7:11:08 AM Pacific Standard Time,
Shalom.Bresticker@motorola.com writes:
> This is not synthesizable. Shalom
> VhdlCohen@aol.com wrote:
> >> My mistake on this. Verilog DOES allows that style: Example:
>> module n ;
>> wire clk, d;
>> reg q; always @(posedge clk) begin
>> q <= 0;
>> @(posedge clk) q <= 1;
>> @(posedge clk) q <= d;
>> end
>> endmodule
>>
>>
> --
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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