Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Wed Dec 12 2001 - 06:54:09 PST
This is not synthesizable.
Shalom
VhdlCohen@aol.com wrote:
> My mistake on this. Verilog DOES allows that style: Example:
> module n ;
> wire clk, d;
> reg q;
>
> always @(posedge clk) begin
> q <= 0;
> @(posedge clk) q <= 1;
> @(posedge clk) q <= d;
> end
> endmodule
-- Shalom Bresticker Shalom.Bresticker@motorola.com Principal Staff Engineer Tel: +972 9 9522268 Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890 POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
This archive was generated by hypermail 2b28 : Wed Dec 12 2001 - 07:00:04 PST