Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: M Ciletti (eagle64@email.msn.com)
Date: Wed Dec 12 2001 - 12:12:48 PST
Xilinx ISE reports an error - that the behavior contains a timing control and an embedded event control. Adding the wrapper, as shown below, leads to a synthesiazable model of the implicit state machine, but it vaporizes unless the pors are added. withthe ports added the tool will build a controlling state machine with wait states.
Mike Ciletti
module n (q, d, clk);
output q;
input d, clk;
//wire clk, d; // redundant
reg q;
always begin:wrapper
@(posedge clk) begin
q <= 0;
@(posedge clk) q <= 1;
@(posedge clk) q <= d;
end
end // wrapper
endmodule
----- Original Message -----
From: Shalom Bresticker
Cc: vlog-synth@eda.org
Sent: Wednesday, December 12, 2001 7:54 AM
Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
This is not synthesizable.
Shalom
VhdlCohen@aol.com wrote:
My mistake on this. Verilog DOES allows that style: Example:
module n ;
wire clk, d;
reg q;
always @(posedge clk) begin
q <= 0;
@(posedge clk) q <= 1;
@(posedge clk) q <= d;
end
endmodule
--
Shalom Bresticker Shalom.Bresticker@motorola.com
Principal Staff Engineer Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
This archive was generated by hypermail 2b28 : Wed Dec 12 2001 - 12:21:12 PST