Subject: FYI: Initialization of RAM
From: VhdlCohen@aol.com
Date: Wed Dec 12 2001 - 10:54:32 PST
Thought this newsgroup clipping would be of interest in our thought on
initializing RAMs.
Ben
-----
Subject: Re: Initialization of RAM
From: Ray Andraka <A HREF="mailto:ray@andraka.com">ray@andraka.com</A>
Date: 12/11/01 7:06 PM Pacific Standard Time
Message-id: <3C16CA10.9E5B812C@andraka.com>
Simon, and Rick,
I think you guys are jumping to conclusions. No one said that the RAM was
even
software accessible, or if it is it may be for a reprogrammable state machine
that has to start up with a default program. There are many reasons for
wanting to initialize a block RAM (or in the case of Altera, an EAB). For
that
matter, the same initialization problem occurs when these blocks are used as
ROM.
The message he is getting indicates that perhaps he already has figured out
how
to initialize it for simulation (that is done through generics on the
instantiated component). The initialization done with generics does not flow
through to the edif netlist, and therefore is not available for the place and
route. For xilinx, you can attach INIT= attributes to the component instance
with the initialization in it to pass the init values to the netlist. The
gotcha there is the init generics are bitvectors and the INIT= attributes are
hex strings, so you need to be careful about how you do it. You can also
generate initial values to be added thorugh the ucf, although I have not done
it that way (the instance names have to be static and known). There is a
similar mechanism for Altera, although I do not recall the name of the
attribute or the format.
If the memory is strictly read-only (ie. a ROM), Synplicity will infer the
ROM
and put the correct attributes on it to initialize it. If you can't find the
information elsewhere, you could infer a ROM in the Altera device, and then
examine the edif netlist to find the name and format of the initialization
attributes for Altera. The same name and format will apply to a RAM.
"S. Ramirez" wrote:
> "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message
> news:3C16BA88.96F9E549@algor.co.uk...
>
> > Don't do it. To be precise it is by far the best practice to make sure
> that
> > during simulation startup all RAMs are initialised to unknowns since ....
> > ... IMO This "feature" is very dangerous and using it will make the code
> > highly non-portable. It also encourages s/w engineers to be sloppy & not
> > initialise RAMs before using them leading to some really deep and hard to
> > trace bugs later on.
>
> Rick,
> What's wrong with initializing RAMs to all zeros? That way, you get a
> known simulation, but you also make the SW engineers initialize the RAMs,
> since all zeros is mostly useless. At least the hardware will come up in a
> known state.
> Simon Ramirez, Consultant
> Synchronous Design, Inc.
> Oviedo, FL USA
-- --Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com <A HREF="http://www.andraka.com">http://www.andraka.com>"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759
Subject: Re: Initialization of RAM From: Roberta Crescentini <A HREF="mailto:roberta.crescentini@alcatel.it">roberta.crescentini@alcatel.it</A> Date: 12/12/01 2:39 AM Pacific Standard Time Message-id: <3C1733EE.F32D74E5@alcatel.it>
Hi if you want to use a ram you can generate the functional vhdl using Altera Megawizard (in Maxplus-Quartus or HdlDesigner ). To initialize it use a hex (intel format) file that you can generate in Maxplus-Quartus and it's required by Megawizard. Then you can simulate the initialized ram.
In the netlist file, the path of hex file is got and, if correct, Maxplus initializes the ram on chip using it. If it doesn't find the hex file, Max-Quartus initialize the ram in some devices (Flex, Apex etc) to a 0 value.
bye
Roberta
---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 <A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------
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