Subject: Fwd: Implicit FSMs style with mutiple clocks
From: VhdlCohen@aol.com
Date: Wed Dec 12 2001 - 13:45:33 PST
CLiff,
Thanks for your detailed explanation. The subject came up because the VHDL
synthesis group is considering it.
Ben Cohen
attached mail follows:
Hi, Ben -
I have been aware of implicit FSM coding styles for years. In general, I
think the style is highly flawed. As long as you have a state machine that
transitions through the same set of states independent of any inputs
(referred to as an autonomous clock machine by Zvi Kohavi - Switching and
Finite Automata Theory - McGraw Hill, 1978, ISBN 0-07-035310-7, p. 401) the
implicit style works fine. If the FSM has any interconnecting transition
arcs between multiple states, the coding style falls apart. I don't even
teach implicit FSM coding styles in my classes because it only addresses a
very small subset of FSM designs and is no more efficient than typical
Verilog FSM coding styles.
Unless a coding style offers a distinct advantage over other more
established coding styles, I see no reason to confuse the issue (and the
students) with multiple styles that all accomplish the same goal,
especially if other styles are more generally better suited to the task,
like the two always block style that I always teach.
I would oppose any initiative to add yet another, highly limited, FSM
coding style to either the IEEE Verilog Synthesis spec or the Accellera
SystemVerilog spec. I see no reason to codify another bad coding style.
Thanks for the question. It is rarely asked and it gave me chance to record
my thoughts on the matter for inclusion in my FSM design notes.
Regards - Cliff
At 02:13 PM 12/12/01 -0500, VhdlCohen@aol.com wrote:
>Cliff,
>I saw your recent post on "FSM Enhancement Goals and Thoughts".
>What about implicit FSMs with multiple @ (posedge clk) in an always block?
>Below is not quite an FSM, but you can get the gest of it. AT every
>clock, you jump to another state. IF statements can also be included.
>
>module n ;
> wire clk, d, c;
> reg q, q2;
>
> always @(posedge clk) begin
>q <= 0;
>@(posedge clk) q <= 1;
> q2<=d;
>
>@(posedge clk)
> if (c) q <= 0;
> else q <= 1;
>end
>
>endmodule
>
>In a message dated 12/12/01 10:09:23 AM Pacific Standard Time,
>dennisb@Model.com writes:
>>RE: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper:
>>Date:12/12/01 10:09:23 AM Pacific Standard Time
>>From:<mailto:dennisb@Model.com>dennisb@Model.com
>>To:<mailto:VhdlCohen@aol.com>VhdlCohen@aol.com
>>CC:<mailto:jbhasker@cadence.com>jbhasker@cadence.com
>>Sent from the Internet
>>
>>
>>
>>Ben,
>>
>> Have you seen or monitored the Verilog++ group's proposed FSM
>> extensions? You can see an email trail at
>> <http://www.eda.org/vlog-pp/hm/>http://www.eda.org/vlog-pp/hm/. In the
>> spirit of harmonization, it might be wise to have the VHDL/Verilog
>> synthesis team look at this too. (I know Cliff Cummings is doing this,
>> so this may be enough, I don't know.)
>>
>>-Dennis
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