Subject: Re: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper
From: VhdlCohen@aol.com
Date: Wed Dec 12 2001 - 06:26:58 PST
In a message dated 12/12/01 1:10:31 AM Pacific Standard Time,
jim@SynthWorks.com writes:
> > Section 2.8
> > Implicit FSM cannot be done in Verilog. Sounds like a good idea since
> > this is done in behavioral synthesis. Verilog group, comments?
> Speaking as a logic designer and as the one who wrote the UartTx
> problem, this coding style is extremely inflexible and I would do not
> expect to be using it in my design practice.
>
My mistake on this. Verilog DOES allows that style: Example:
module n ;
wire clk, d;
reg q;
always @(posedge clk) begin
q <= 0;
@(posedge clk) q <= 1;
@(posedge clk) q <= d;
end
endmodule
Sorry guys ... sometimes we're in another world!!!
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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