Subject: VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper:
From: VhdlCohen@aol.com
Date: Tue Dec 11 2001 - 21:23:08 PST
VHDL Group: Attached are my comments.
Verilog group: SUMMARY:
I would recommend that the Verilog and VHDL synthesis interoperability group
converge into a comment set of coding templates and attributes. That
convergence would make the process of adapting to these new standard more
palatable for synthesis vendors. We, in each group, see our own HDL, our own
world, and come up with some ingenious styles and attributes that make it
more difficult to for vendors to adopt both of these recommendations. These
variations also make it difficult to translate code from one HDL into the
other. If I have to guess at to which HDL standard vendors would first
adopt, it's the Verilog standard because synthesis vendors have more Verilog
licenses than VHDL licenses (some may disagree here). Vendors may never
adopt the VHDL new standard if it is so far apart from the Verilog standard.
Attached document, and Jim's HDL CON draft provide all of my comments
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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In a message dated 12/11/01 10:18:24 AM Pacific Standard Time,
jim@SynthWorks.com writes:
> Hi,
> Vinaya and I have been working on a paper for HDLCon. It contains
> mistakes, lies, and mis-truths about the current work on 1076.6.
> We would like your help in finding and removing any issues before we
> have to turn in the final draft in January.
>
> Just kidding about the lies and mis-truths. Any constructive
> input appreciated. Particularly examples that show new features that
> you are excited about. Our goal is to show VHDL users how they will
> benefit from the new standard and hopefully motivate them to nag their
> EDA vendor into supporting 1076.6 and other relevant VHDL standards
> (so I dream a little - it is late after all).
>
> -----------------------------------------------------------------------
> This is now part of a resend. It does not look like the email
> with paper attachment made it out of the reflector. So I put the paper
> on my website for your viewing pleasure:
>
> http://www.synthworks.com/vhdlRTLStandard_r6.pdf
>
> Note: either the above link or make sure you have the case correct on
> the name of the pdf file.
>
> Note that this is a draft copy of the paper. In particular,
> Sections 5, 6, and 7 are still being worked on. Again any constructive
> input is appreciated (particularly in the sections above).
> -----------------------------------------------------------------------
>
>
> Cheers,
> Jim
> --
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Jim Lewis
> Director of Training mailto:Jim@SynthWorks.com
> SynthWorks Design Inc. http://www.SynthWorks.com
> 1-503-590-4787
>
> Expert VHDL training with a focus on hardware design and test.
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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