RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01

Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01
From: J. Bhasker (jbhasker@cadence.com)
Date: Tue Dec 11 2001 - 09:56:59 PST

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Here are the meeting minutes:

Attendees:
  Paul Graham
  Ben Cohen
  J. Bhasker
  Cliff Cummings
  Stefan Boyd

1. Cliff discussed his updated draft. All updates were accepted.

2. The list of attributes still need to be discussed and agreed upon.
   Cliff to contact Synopsys to see what attributes they would like to
donate.
   Ben to contact Synplicity and try to get their attributes.
   Paul already presented Cadence attributes - however he will add more
information on what
   each of the attribute does before the next meeting.

3. The plan at the next meeting is to consolidate all the attributes recd
till then and discuss these.
Most probably we will not accept any more attributes after the next
meeting.

4. Discussed updated Ben's proposal on ROM modeling. It was argued that the
function/task style
was really not required (since there were already two other approaches).
Ben agreed to withdraw
the function/task style modeling of ROMs.

5. Bhasker to consolidate Ben's final proposal and Cliff's updated proposal
into the next rev
of the synthesis draft (D1.8).

6. Next WG meeting we plan to discuss the set of attributes and then start
reviewing the draft standard.

7. Next meeting dates: Jan 11 2002, Feb 8 2002.

- bhasker

J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com

-----Original Message----- From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of J. Bhasker Sent: Monday, December 03, 2001 1:55 PM To: vlog-synth@eda.org Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01

The next Verilog Synthesis Interoperability Working Group phone conference is scheduled for FRIDAY, DECEMBER 7 from 12:00pm to 1:30pm EASTERN STANDARD TIME.

Call: USA Toll Free Number: 888-566-5909 USA Toll Number: +1-630-395-0202 PASSCODE: 14202 LEADER: J. Bhasker

Agenda:

1. To discuss synthesis attributes as proposed in Cliff's proposal. From the last meeting minutes - IF YOU SEE AN ATTRIBUTE THAT YOU WOULD LIKE TO SEE STANDARDIZED, PLEASE PROVIDE A WRITE UP OF ITS SEMANTICS AND USAGE - else it is most likely to be removed. Cliff to lead the discussion.

2. To continue to discuss RAM and ROM modeling based on his latest proposal - BenCohen.

Future telecon dates: Jan 11, 2002.

Regards,

- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com) Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth

Next message: VhdlCohen@aol.com: "VHDL extensions and styles pertinent to Verilog + Re: HDL Con Paper:"
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