Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01

Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Mon Dec 03 2001 - 10:54:50 PST

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The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, DECEMBER 7 from 12:00pm to
1:30pm EASTERN STANDARD TIME.

Call:
 USA Toll Free Number: 888-566-5909
 USA Toll Number: +1-630-395-0202
  PASSCODE: 14202
  LEADER: J. Bhasker

Agenda:

1. To discuss synthesis attributes as proposed in Cliff's proposal. From the
last meeting
   minutes - IF YOU SEE AN ATTRIBUTE THAT YOU WOULD LIKE TO SEE
   STANDARDIZED, PLEASE PROVIDE A WRITE UP OF ITS SEMANTICS AND USAGE - else
it is
   most likely to be removed. Cliff to lead the discussion.

2. To continue to discuss RAM and ROM modeling based on his latest
proposal - BenCohen.

Future telecon dates: Jan 11, 2002.

Regards,

- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
  Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
  Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth

• Next message: Clifford E. Cummings: "D1_7 Pragmas Proposal - Section 6 - (updated 20011206)"
• Previous message: VhdlCohen@aol.com: "Re: New proposal for ROM definitions in functions and tasks"
• Reply: J. Bhasker: "RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Dec 7, '01"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

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