Subject: Re: Initial Blocks fail with Synopsys Tools
From: VhdlCohen@aol.com
Date: Sat Oct 06 2001 - 09:57:19 PDT
For the record, Synplify provides WARNINGS! Below is portion of report:
$ Start of Compile
#Sat Oct 06 09:54:48 2001
Synplicity Verilog Compiler, version 6.2.0, Build 097R, built Apr 16 2001
Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved
@I::"c:\__dsgn\dff.v"
Verilog syntax check successful!
Selecting top level module dff
Synthesizing module dff
@W:"c:\__dsgn\dff.v":6:3:6:9|Ignoring initial statement
@END
In a message dated 10/5/01 6:07:38 PM Pacific Daylight Time,
cliffc@sunburst-design.com writes:
> I was very surprised to learn that Synplicity ignored initial blocks. I
> consider this to be a serious flaw in the Synplicity tools.
>
> module dff (q, d, clk, rst_n);
> output q;
> input d, clk, rst_n;
> reg q;
>
> initial q <= 0;
>
> always @(posedge clk or negedge rst_n)
> if (!rst_n) q <= 1'b0;
> else q <= d;
> endmodule
>
>
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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