Subject: Another attribute: test_port
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Wed Mar 27 2002 - 08:27:09 PST
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[BEN] Let's rewrite the "probe" as:
probe :
This attribute preserves internal net for probing causing them to appear as ports on the top level of the hierarchy being synthesized.
// comment to panel. This attribute is needed for the verification of gate-level model designs ot the "grey-box" level where internal signals may be needed for triggering of events in verifier (example, the occurrence of a simulatation push/pop of a fifo. It is also needed for hardweare debugging when a difficult bug occurs.
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After further discussions with Ben on the intent of this attribute,
I have rewritten the attribute semantics and renamed the attribute:
+++++++++++++++++++++++++
(* synthesis, test_port [ =<optional_value> ] *)
This attribute shall apply to a net or a reg.
The presence of this attribute preserves the net or the reg for probing and
shall cause it to appear as an output port (a test port) in
the module it appears. If a module with a test port
is instantiated in another module, a new test port
shall also be created (one for each instance) in the parent module.
In the case where the reg infers a storage device, it is the output of the
storage device that shall be used to create the test port.
Note: This attribute is needed for the verification of gate-level model designs at the "grey-box" level where internal signals may be needed for triggering of events in verifier (example, the occurrence of a simulatation push/pop of a fifo). It may also needed for hardware debugging when a difficult bug occurs.
Note: Since this attribute creates additional ports in the synthesized logic,
testbench reuse may be an issue.
+++++++++++++++++++++++++++
Please post comments within a week.
- bhasker
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