Re: Another attribute: test_port


Subject: Re: Another attribute: test_port
From: VhdlCohen@aol.com
Date: Thu Mar 28 2002 - 11:12:32 PST


In a message dated 3/28/02 11:02:02 AM Pacific Standard Time,
pbryant@innoveda.com writes:

> I disagree that you remove if can be optimized out. It should remain, for
> the intent
> was that it me present for a test point.
>
  
If you need to keep the object, then add the "keep" attribute to the
"test_port" attribute.
Issue: If I declare a reg with a "test_port" attribute, and that reg is ne
ver used, it should be optimized out, unless there is a "keep".

I said:
If a test ported attributed object is optimized out, that object shall not be
mapped onto a port.

Purpose is to bring a test point out.
I could do something like:
  wire q ; // with the test_port and keep attributes, I can't remember syntax
here
  assign q = mem[addr];

> Just my $.02 worth.
>
> Pat
>
> >> -----Original Message-----
>> From: VhdlCohen@aol.com [mailto:VhdlCohen@aol.com]
>> Sent: Thursday, March 28, 2002 10:39 AM
>> To: kal@dspia.com
>> Cc: vlog-synth@eda.org
>> Subject: Re: Another attribute: test_port
>>
>>
>>
>> A few comments:
>> Change from:
>> "In the case where the reg infers a storage device, it is the output of
>> the storage device that shall be used to create the test port."
>>
>> TO:
>> Only objects that represents bits or bit vectors shall be used to create
>> the test port.
>>
>> Rationale: It might be difficult for a tool to determine the "output of a
>> storage device".
>>
>> ADD:
>> If a test ported attributed object is optimized out, that object shall not
>> be mapped onto a port.
>>
>

----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------



This archive was generated by hypermail 2b28 : Thu Mar 28 2002 - 11:16:27 PST