Subject: Updated 1364.1 v2.1 draft available
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Fri Mar 29 2002 - 07:47:59 PST
V2.1 of the Verilog RTL Synthesis draft is now available on
our web site (http://www.eda.org/vlog-synth).
Changes made (change bars show diff from previous version):
- updated Annex B with new material provided by CliffC - made changes that I & SteveG
had recommended.
- added the new test_port attribute (havent made any changes from my proposal - I saw
a flurry of emails after I posted the draft) - lets discuss the changes at our next
WG meeting.
- added more material to introduction
- corrected typos pointed out by DanJ.
- corrected typos pointed out by MuzaffarK.
- updated keep attribute semantics as per BenC.
- also fixed typos, grammar pointed out by BenC.
PLEASE REVIEW DRAFT. DEADLINE FOR POSTING FINAL FEEDBACK IS APRIL 5. After that we get into
IEEE standardization process ...
- bhasker
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
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