Subject: Re: Another attribute: test_port
From: VhdlCohen@aol.com
Date: Wed Mar 27 2002 - 09:07:16 PST
Bhasker,
I like your write up and the notes!
FYI, can use the ifdef to use the path to read internal signals if RTL, or
test port if gate level.
Don't know if you want to add that note.
Ben
-- In a message dated 3/27/02 8:53:29 AM Pacific Standard Time, jbhasker@cadence.com writes:> (* synthesis, test_port [ =<optional_value> ] *) > > This attribute shall apply to a net or a reg. > > The presence of this attribute preserves the net or the reg for probing and > shall cause it to appear as an output port (a test port) in > the module it appears. If a module with a test port > is instantiated in another module, a new test port > shall also be created (one for each instance) in the parent module. > > In the case where the reg infers a storage device, it is the output of the > storage device that shall be used to create the test port. > > Note: This attribute is needed for the verification of gate-level model > designs at the "grey-box" level where internal signals may be needed for > triggering of events in verifier (example, the occurrence of a simulatation > push/pop of a fifo). It may also needed for hardware debugging when a > difficult bug occurs. > > Note: Since this attribute creates additional ports in the synthesized > logic, > testbench reuse may be an issue. > >
---------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 <A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------
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