Subject: Verilog RTL Synthesis Interoperability WG meeting: Feb 8, 2002
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Mon Feb 04 2002 - 11:13:19 PST
The next Verilog RTL Synthesis Interoperability WG teleconference is scheduled
for FEB 8, 2002 from 12:00pm to 1:30pm.
Here are the call details:
CALL DATE: FEB-08-2002 (Friday)
CALL TIME: 12:00 PM EASTERN TIME
DURATION: 1 hr 30 min
USA Toll Free Number: 888-469-3061
USA Toll Number: +1-712-271-3820
PASSCODE: 39333
LEADER: Mr Jayaram Bhasker
Agenda:
1. Cliff to present additional attributes.
2. Bhasker - IEEE new template for draft/standard.
3. Bhasker - brief overview of standardization process.
4. Any draft review comments for discussion.
The WG meeting in March is likely to be a face-to-face meeting during HDLCON
in Santa Clara (Mar 11-12) - more details later.
Regards,
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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