Subject: Re: Looking for peace in the VHDL and Verilog Attributes
From: Paul Graham (pgraham@Cadence.COM)
Date: Thu Jun 13 2002 - 14:00:10 PDT
> Out of curiosity, why did you depricate it? Is (`ifdef SYNTHESIS)
> safer from a methodology sense than "//synthesis translate_off"?
> I understand that (`ifdef SYNTHESIS) is cooler, but I would not
> be motivated to depricate an equally safe methodology.
The difference is that
// synthesis translate_off
has no effect on a simulator, and so can result in differences between
synthesis and simulation. But
`ifndef SYNTHESIS
can be handled by a simulator (if you run it with -DSYNTHESIS), so you can
simulate the exact design that you are synthesizing.
Not just a simulator, but any verilog tool should be able to handle `ifdefs.
Paul
This archive was generated by hypermail 2b28 : Thu Jun 13 2002 - 14:11:54 PDT