Subject: Re: Looking for peace in the VHDL and Verilog Attributes
From: Clifford E. Cummings (cliffc@sunburst-design.com)
Date: Thu Jun 13 2002 - 14:27:48 PDT
Hi, all -
John's interpretation is not bad.
In reality, `ifdef SYNTHESIS or `ifndef SYNTHESIS is actually a super-set
of translate_off and translate_on.
// synopsys translate_off
// Verilog simulation-only code
// synopsys translate_on
is easily replaced with:
`ifndef SYNTHESIS
// Verilog simulation-only code
`endif
(bonus - this is less verbose)
But now you can add code that is only recognized by synthesis tools:
`ifdef SYNTHESIS
// synthesis-only Verilog code
`endif
Whether or not this is a good idea is to be determined.
You can also easily choose between synthesis-only Verilog and
simulation-only Verilog:
`ifdef SYNTHESIS
// synthesis-only Verilog code
`else
// simulation-only Verilog code
`endif
You could also setup synthesis-only -vs- coverage-only Verilog code:
`ifdef SYNTHESIS
// synthesis-only Verilog code
`elsif COVERAGE // not defined by any standard that I know of
// coverage-only Verilog code
`endif
When we were deciding to NOT add (* synthesis, translate_off *) and (*
synthesis, translate_on *), I still thought the latter would be needed so I
took the action item to find a reason to add these attributes to Verilog
synthesis. I could find no example that was not covered by the ifdef method.
Even though translate_off/_on is not defined by any standard, it is so
commonly used that we felt it was a good idea to disclose the thinking of
the Verilog synthesis committee by deprecating a de facto standard.
Deprecating means that the functionality may not be supported by all tools
in the future and that the standards body does not expect the functionality
to be supported. It is then the vendors choice to support or not. Without
deprecating translate_off, we would receive hundreds of emails asking why
we did not add translate_off to Verilog synthesis. Deprecating gave us a
chance to say, "don't do this, but do this instead."
Regards - Cliff
At 01:35 PM 6/13/02 -0700, John Michael Williams wrote:
>Hi Jim.
>
>Jim Lewis wrote:
> >
> > It is my opinion that the VHDL and Verilog attributes should
> > be more similar. Before you lock your mind into it can't be
> > done, read the following, I think we have more in common than
> > you think. Keep in mind here, I am only speaking for myself,
> > but I would like to offer this as a starting point for
> > discussion.
> >
> > First lets look at the attribute syntax
> > ...
> > Out of curiosity, why did you depricate it? Is (`ifdef SYNTHESIS)
> > safer from a methodology sense than "//synthesis translate_off"?
> > I understand that (`ifdef SYNTHESIS) is cooler, but I would not
> > be motivated to depricate an equally safe methodology.
> > ...
>
>I think the `ifdef SYNTHESIS shouldn't be viewed in
>isolation. The ifdef's are multitudinous in Verilog
>and are inherited from its C language base: In C or
>C++, #ifdef conditionally invokes a macro preprocessor
>which can modify the code before the parser is invoked.
>Likewise, `include (filename).
>
>On the other hand, I can't think of any commented code
>in C or C++ which does anything. So, dropping a
>couple of comments from Verilog which are INconsistent
>with C and C++ is advantageous. At least, that is how I
>would interpret the decision.
>--
> John
> jwill@AstraGate.net
> John Michael Williams
----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, Synthesis and Verification Training
This archive was generated by hypermail 2b28 : Thu Jun 13 2002 - 14:42:40 PDT