Subject: Re: Looking for peace in the VHDL and Verilog Attributes
From: John Michael Williams (jwill@AstraGate.net)
Date: Thu Jun 13 2002 - 13:35:24 PDT
Hi Jim.
Jim Lewis wrote:
>
> It is my opinion that the VHDL and Verilog attributes should
> be more similar. Before you lock your mind into it can't be
> done, read the following, I think we have more in common than
> you think. Keep in mind here, I am only speaking for myself,
> but I would like to offer this as a starting point for
> discussion.
>
> First lets look at the attribute syntax
> ...
> Out of curiosity, why did you depricate it? Is (`ifdef SYNTHESIS)
> safer from a methodology sense than "//synthesis translate_off"?
> I understand that (`ifdef SYNTHESIS) is cooler, but I would not
> be motivated to depricate an equally safe methodology.
> ...
I think the `ifdef SYNTHESIS shouldn't be viewed in
isolation. The ifdef's are multitudinous in Verilog
and are inherited from its C language base: In C or
C++, #ifdef conditionally invokes a macro preprocessor
which can modify the code before the parser is invoked.
Likewise, `include (filename).
On the other hand, I can't think of any commented code
in C or C++ which does anything. So, dropping a
couple of comments from Verilog which are INconsistent
with C and C++ is advantageous. At least, that is how I
would interpret the decision.
--
John
jwill@AstraGate.net
John Michael Williams
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