Subject: Re: Please vote yes - 1364.1 ballot
From: David Bishop (dbishop@server.vhdl.org)
Date: Wed Jun 12 2002 - 17:54:59 PDT
Forwarde e-mail from Jim Lewis:
Date: Wed, 12 Jun 2002 15:22:36 -0700
From: Jim Lewis <jim@synthworks.com>
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To: "Clifford E. Cummings" <cliffc@sunburst-design.com>
Subject: Re: Please vote yes - 1364.1 ballot
Cliff,
One thing I would like to see change with the IEEE ballot process
is to make ballot comments public so if other people agree, they can
reinforce the comments the other balloters have made. Or after the
initial ballot, the comments and responses become public and a person
is permitted to change their ballot based on the comment and resolution
of someone elses vote.
I have the following issue with 1364.1. If there is one place
that Verilog and VHDL should agree, it should be on the naming of
the synthesis attributes (at least those are similar or overlapping
in meaning). The benefit will be a large for those who use both
languages in their design flow. To make this happen, a coordinated
effort is required.
Hence, I have voted no (with comments) and requested that both
groups get together and find a common set of attributes. I am not
saying one or the other group is right, I am just saying both groups
should have a say in this.
Cheers,
Jim
"Clifford E. Cummings" wrote:
>
> Hi, All -
>
> This email is to IEEE1364.1 balloters whom I know.
>
> I would like to encourage you to vote "YES" on the IEEE 1364.1 ballot, due
> tomorrow, June 13th.
>
> Many of you have been through the IEEE Standards process before and so I
> would also like to encourage as many of you to vote "YES, without comment"
> as I can to reduce the amount of work the IEEE 1364.1 committee will have
> to do to respond to ballots after voting has completed.
>
> I am very pleased with the content of and effort that went into this
> proposed standard. Hopefully the standard will encourage vendors to support
> a very good subset of the Verilog-2001 standard for synthesis.
>
> Your "YES, without comment" vote would be greatly appreciated.
>
> Best Regards - Cliff Cummings
>
> At 01:49 PM 6/3/02 -0400, Jayaram Bhasker wrote:
> >Dear IEEE P1364.1/D2.2 Balloting Group Member:
> >
> >This e-mail is to advise you of the opening of the electronic
> >ballot for IEEE P1364.1/D2.2. Instructions for accessing the
> >draft standard and for casting your votes and comments follow.
> > ------------------------------------------------
> >
> >****INSTRUCTIONS FOR BALLOTING ON: IEEE P1364.1/D2.2
> >"Draft Standard for Verilog Register Transfer Level
> >Synthesis"****
> >
> >The electronic ballot for IEEE P1364.1/D2.2 officially opens on
> >Wednesday, 15-May-2002, and it closes at 11:59 p.m. (Eastern
> >Time) on Thursday, 13-June-2002.
> >
> >Please review the information below regarding the balloting
> >procedures.
> >
> >A copy of this draft can be found at the following
> >password-protected website (URL):
> >
> >http://grouper.ieee.org/groups/ballot/p1364_1/
> >
> >User ID: 13641bal (note: this is case sensitive)
> >Password: one36for (note: this is case sensitive)
> >
> >The draft is posted in Adobe "pdf" document format and can be
> >viewed online, or it can be downloaded and printed if desired.
> >You will need a copy of Adobe's Acrobat Reader (3.0 or higher)
> >to view or print the draft. If you do not have this program,
> >it is available for free downloading from Adobe at:
> >(http://www.adobe.com/prodindex/acrobat/readstep.html).
> >
> >This draft is posted for your review for balloting purposes
> >only, and should not be copied or redistributed. Downloading
> >time may be affected due to the size of the draft.
> >
> >You should cast your electronic vote on this draft at the
> >following website:
> >http://standards.ieee.org/cgi-bin/balloting?vote:0000226
> >
> >Comments on the draft should be entered at the following
> >website:
> >http://standards.ieee.org/cgi-bin/balloting?comment:0000226
> >
> >If you should have any questions, problems or comments please
> >contact the Working Group Chair:
> >
> >Jayaram Bhasker
> >Phone:610-398-6312
> >Fax: 610-530-7985
> >Email: jbhasker@cadence.com
> >
> >***REMINDER: THE BALLOT CLOSES AT 11:59 P.M., 13-June-2002****
> >The voting and comment web sites will be shut down at this time,
> >and no votes and/or comments will be accepted after this point.
> >
> >Thank you for your participation in this ballot. We appreciate
> >your cooperation in this program, and welcome your comments and
> >suggestions for improvements.
> >
> >IEEE-SA Balloting Center
>
> ----------------------------------------------------
> Cliff Cummings - Sunburst Design, Inc.
> 14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
> Phone: 503-641-8446 / FAX: 503-641-8486
> cliffc@sunburst-design.com / www.sunburst-design.com
> Expert Verilog, Synthesis and Verification Training
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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