Verilog RTL Synthesis, Semantics Section 4.

Ken Coffman (kcoffman@sos.net)
Mon, 07 Sep 1998 17:39:52 -0700

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Here's the latest revision of P1364.1, section 4. I think we're making
progress.
- Regards.
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{\title Section 4 Modeling Hardware Elements}{\author Ken Coffman}{\operator Ken Coffman}{\creatim\yr1998\mo9\dy7\hr16\min48}{\revtim\yr1998\mo9\dy7\hr16\min48}{\printim\yr1998\mo9\dy7\hr15\min17}{\version2}{\edmins0}{\nofpages8}{\nofwords1868}
{\nofchars10651}{\*\company Bytech Services}{\nofcharsws13080}{\vern71}}\widowctrl\ftnbj\aenddoc\makebackup\hyphcaps0\viewkind1\viewscale100 \fet0\sectd \linex0\sectdefaultcl {\header \pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
IEEE P1364.1
\par BASED ON THE VERILOG \'ae HARDWARE DESCRIPTION LANGUAGE June 3, 1998
\par Section 4 Copyright @ 1998 IEEE. All rights reserved. 11
\par }{\cgrid0 This is an unapproved IEEE Standards Draft, subject to change.
\par }{
\par }}{\*\pnseclvl1\pnucrm\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl2\pnucltr\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl3\pndec\pnstart1\pnindent720\pnhang{\pntxta .}}{\*\pnseclvl4\pnlcltr\pnstart1\pnindent720\pnhang{\pntxta )}}
{\*\pnseclvl5\pndec\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl6\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl7\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl8
\pnlcltr\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}{\*\pnseclvl9\pnlcrm\pnstart1\pnindent720\pnhang{\pntxtb (}{\pntxta )}}\pard\plain \nowidctlpar\outlinelevel0\adjustright \fs20\cgrid {\b\cf1\cgrid0 Section 4 Modeling Hardware Elements
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {
This section describes styles for modeling hardware elements such as edge-sensitive storage devices, level-sensitive storage devices (latches), and three-state drivers. This standard does not specify or limit optimization.
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
The hardware inferences specified in this section do not take into account optimizations or transformations. A specific tool may perform optimization and not generate the suggested hardware inferences or generate a different set of hardware inferences.
This shall }{\i\cf1\cgrid0 not }{\cf1\cgrid0 be taken as a violation of this standard provided the synthesized netlist has the same functionality as the input model.
\par
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\b\cf1\cgrid0 4.1 Modeling Combinational Logic
\par }\pard \nowidctlpar\adjustright {\cgrid0 A combinational logic event sensitivity list contains a variable or a list of variables separated by the keyword }{\b\cgrid0 or}{\cgrid0 . }{\cf1\cgrid0 If the event sensitivity list of an }{\b\cf1\cgrid0 always }{
\cf1\cgrid0 statement lists all input variables (which will appear in right-hand side expressions in the }{\b\cf1\cgrid0 always}{\cf1\cgrid0 statement body), its event sensitivity list is said to be }{\i\cf1\cgrid0 complete}{\cf1\cgrid0 .
\par }{\cgrid0 Expressions inside the always statement body will be evaluated by a Verilog simulator when any variable in the sensitivity list changes value. }{
The event sensitivity list for a combinational logic construct does not affect synthesized logic. However, it is important that the sensitivity list be complete to insure that simulation and synthesis results match.
\par
\par }{\b EDITORS NOTE:}{ Shall we allow the use of }{\b always @}{ (*) to infer a complete list of variables?
\par
\par T}{\cf1\cgrid0 he event sensitivity list for a combinational logic construct must not contain the reserved words }{\b\cf1\cgrid0 posedge }{\cf1\cgrid0 or }{\b\cf1\cgrid0 negedge }{\cf1\cgrid0
or anything other than variables used as inputs inside the always statement body.
\par Not all variables that appear in the right hand side of an assignment are required to appear in the event sensitivity list. Vari
ables that are assigned values inside the always statement body before being used by other expressions do not have to appear in the event sensitivity list.}{\b\cf1\cgrid0
\par
\par }{\i\cf1\cgrid0 Example 4.1.1}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always}{\cf1\cgrid0 }{\b\cf1\cgrid0 @}{\cf1\cgrid0 (OP1 }{\b\cf1\cgrid0 or}{\cf1\cgrid0 OP2) // Legal
\par ...
\par
\par }{\i\cf1\cgrid0 Example 4.1.2}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (BUSA[11] }{\b\cf1\cgrid0 or}{\cf1\cgrid0 BUSB[7:2]) // Legal
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {...
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.1.3}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always}{\cf1\cgrid0 }{\b\cf1\cgrid0 @ }{\cf1\cgrid0 (A + B) // Not supported because logical constructs are not
\par // allowed in the event sensitivity list.
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {...
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.1.4}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 A[B]) // Not supported because bit-selected variables
\par // are not allowed for clock or control.
\par ...
\par
\par }{\i\cf1\cgrid0 Example 4.1.5}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN1 }{\b\cf1\cgrid0 or}{\cf1\cgrid0 IN2) // Legal because all input variables are specified.
\par OUT = IN1 + IN2;
\par \'85
\par
\par In Example 4.1.6, the register variable TMP is not required to appear in the event sensitivity list since it is assigned before it is used in the always block.
\par
\par }{\i\cf1\cgrid0 Example 4.1.6}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN) // TMP is not required in the event sensitivity list
\par // because it is assigned a value before being used.
\par }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 TMP = IN;
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 OUT = TMP;
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par In Example 4.1.7, signals IN1 and IN2 are not required in the event sensitivity list because the variable OUT will be evaluated only when SEL changes.
\par
\par }{\i\cf1\cgrid0 Example 4.1.7}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (SEL or IN1) // Legal, though IN1 is not required.
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (SEL)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 OUT = IN1; // Legal.
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 else
\par }{\cf1\cgrid0 \tab }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 OUT = IN2; // Legal.
\par
\par }{\i\cf1\cgrid0 Example 4.1.8}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (ENA) // Not supported because ENA should be in the event sensitivity list.
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = IN;
\par
\par In Example 4.1.9, TMP is required in the event sensitivity list because it is used in a non-blocking manner which causes TMP and OUT to be assigned concurrently.
\par
\par }\pard \nowidctlpar\adjustright {\i\cf1\cgrid0 Example 4.1.9}{\cf1\cgrid0 :
\par \tab }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN)
\par \tab }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 \tab TMP <= IN; // Not supported because TMP should be in the event sensitivity list.
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT <= TMP;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par In Example 4.1.10, an error occurs because the same register (OUT) cannot be assigned in both a procedural-continuous and a non procedural-continuous manner in an always statement body.
\par
\par }{\i\cf1\cgrid0 Example 4.1.10}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN1 }{\b\cf1\cgrid0 or}{\cf1\cgrid0 SEL)
\par \tab }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 \tab }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 OUT = IN1; // Procedural-continuous assignment.
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (SEL)
\par \tab }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 OUT = 2; // Non procedural-continuous assignment.
\par \tab }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par In Example 4.1.11, an error occurs because OUT cannot be assigned in both a blocking and a non-blocking procedural manner in an always statement body.
\par
\par }{\i\cf1\cgrid0 Example 4.1.11}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN1 }{\b\cf1\cgrid0 or}{\cf1\cgrid0 IN2 }{\b\cf1\cgrid0 or}{\cf1\cgrid0 SEL)
\par \tab }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 \tab OUT = IN1; // Blocking assignment
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (SEL)
\par \tab OUT <= 2; // Non-blocking assignment.
\par \tab }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\b\cf1\cgrid0 EDITOR\rquote S NOTE:}{\cf1\cgrid0 the following \lquote Z\rquote statements are unverified! Would someone please try this?
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 In Example 4.1.12, note that \lquote Z\rquote assignment(s) will not be propagated across variable assignments.
\par
\par }{\i\cf1\cgrid0 Example 4.1.12}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 ztest;
\par }{\b\cf1\cgrid0 wire}{\cf1\cgrid0 test1, test2, test3;
\par }{\b\cf1\cgrid0 input}{\cf1\cgrid0 test2;
\par }{\b\cf1\cgrid0 output}{\cf1\cgrid0 test3;
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 test1\tab =\tab 1\rquote bz;
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 test3\tab =\tab test1 & test2; // test3 will never receive a \lquote Z\rquote assignment.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.1.13}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (IN)
\par \tab }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 \tab TMP = 'bZ;
\par \tab OUT = TMP; // OUT will never be driven by three state drivers.
\par \tab }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {Example 4.1.14 illustrates how assignment to \lquote Z\rquote may occur in a module and be passed via following port assignments.
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.1.14}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 foo(bar, clock);
\par }{\b\cf1\cgrid0 input}{\cf1\cgrid0 bar, clock;
\par }{\b\cf1\cgrid0 wire}{\cf1\cgrid0 bar, clock;
\par }{\b\cf1\cgrid0 reg}{\cf1\cgrid0 reset;
\par bus1 u1(bar, clock, reset);
\par bus1 u2(bar, clock, reset);
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bus1(bus, clock, reset);
\par }{\b\cf1\cgrid0 input}{\cf1\cgrid0 clock, reset;
\par }{\b\cf1\cgrid0 output}{\cf1\cgrid0 bus;
\par }{\b\cf1\cgrid0 reg}{\cf1\cgrid0 \tab bus;
\par }{\b\cf1\cgrid0 reg}{\cf1\cgrid0 [1:0] state;
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 clock }{\b\cf1\cgrid0 or}{\cf1\cgrid0 }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 reset) }{\b\cf1\cgrid0 begin}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (reset == 1'b1) }{\b\cf1\cgrid0 begin}{\cf1\cgrid0
\par state = 2'b00;
\par }{\b\cf1\cgrid0 end else begin}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 case }{\cf1\cgrid0 (state)
\par 2'b00: }{\b\cf1\cgrid0 begin}{\cf1\cgrid0
\par // ...
\par }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0 2'b01: }{\b\cf1\cgrid0 begin}{\cf1\cgrid0
\par bus = 1'bz;
\par // ...
\par }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0 // ...
\par }{\b\cf1\cgrid0 endcase
\par }{\cf1\cgrid0 }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0 }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0 }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 4.2 Modeling Edge-Sensitive Sequential Logic
\par
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\b\cf1\cgrid0 4.2.1 Clock Specifications
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 When modeling synchronous logic constructs, the reserved words }{\b\cf1\cgrid0 posedge }{\cf1\cgrid0 or }{\b\cf1\cgrid0 negedge }{\cf1\cgrid0
will be used as edge-control specifiers within the event sensitivity list of an }{\b\cf1\cgrid0 always }{\cf1\cgrid0 statement.
\par
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\b\cf1\cgrid0 4.2.1.1 Positive Edge Clock
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 The following represents a positive clock edge expression in an }{\b\cf1\cgrid0 always }{\cf1\cgrid0 statement:
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK)
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {...
\par
\par }\pard\plain \nowidctlpar\outlinelevel0\adjustright \fs20\cgrid {\b\cf1\cgrid0 4.2.1.2 Negative Edge Clock
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 The following represents a negative clock edge expression in an }{\b\cf1\cgrid0 always }{\cf1\cgrid0 statement:
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 negedge}{\cf1\cgrid0 CLOCK)
\par ...
\par
\par }{\b\cf1\cgrid0 4.2.2 Modeling Edge-Sensitive Storage Devices
\par }{\cf1\cgrid0 All edge-sensitive storage devices will be modeled with synchronous assignments to a variable. A synchronous assignment is a variable assignment under the control of a clock.
\par An edge-sensitive storage construct without asynchronous set or reset is be modeled using an }{\b\cf1\cgrid0 always }{\cf1\cgrid0 statement whose event sensitivity list uses either the reserved words }{\b\cf1\cgrid0 posedge }{\cf1\cgrid0 or }{
\b\cf1\cgrid0 negedge }{\cf1\cgrid0 followed by the clock variable. No other variables will be included in the event sensitivity list.
\par
\par }{\i\cf1\cgrid0 Example 4.2.2.1}{\cf1\cgrid0 :
\par // Positive edge triggered edge-sensitive storage device.
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.2.2.2}{\cf1\cgrid0 :
\par // Negative edge triggered edge-sensitive storage device.
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 negedge}{\cf1\cgrid0 CLOCK)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.2.2.3}{\cf1\cgrid0 :
\par // Positive edge triggered edge-sensitive storage device with synchronous reset
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (RESET)
\par \tab OUT = 1'b0;
\par \tab }{\b\cf1\cgrid0 else
\par }{\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par
\par }{\i\cf1\cgrid0 Example 4.2.2.4}{\cf1\cgrid0 :
\par // Positive edge triggered edge-sensitive storage device with synchronous set
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (SET)
\par \tab OUT = 1'b1;
\par \tab }{\b\cf1\cgrid0 else
\par }{\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par
\par
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\b\cf1\cgrid0 4.2.2.1 Edge-Sensitive Storage Device Modeling with Asynchronous Set-Reset
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 An edge-sensitive storage device with an asynchronous set and/or asynchronous reset is modeled using an }{\b\cf1\cgrid0 always }{\cf1\cgrid0 statement whose event sensitivity list contains the reserved words }{
\b\cf1\cgrid0 posedge }{\cf1\cgrid0 or }{\b\cf1\cgrid0 negedge }{\cf1\cgrid0 for the clock and asynchronous variables. A maximum of 3 variables may appear in the event sensitivity list. A mix of level-sensitive and }{\b\cf1\cgrid0 posedge/negedge }{
\cf1\cgrid0 variables is not supported.
\par
\par }{\cgrid0 An }{\b\cgrid0 if }{\cgrid0 condition statement is used with any asynchronous controls and is placed in }{\b\cgrid0 if }{\cgrid0 branches that precede the clock }{
branch. The asynchronous set and or reset logic will therefore have higher priority than the clock variable.
\par }{\cf1\cgrid0
\par In Example 4.2.2.1.1, a flipflop with asynchronous SET is modeled.
\par
\par }{\i\cf1\cgrid0 Example 4.2.2.1.1}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK }{\b\cf1\cgrid0 or}{\cf1\cgrid0 }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 SET)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (SET)
\par \tab OUT <= 1'b1;
\par \tab }{\b\cf1\cgrid0 else
\par }{\cf1\cgrid0 \tab OUT <= DIN;
\par
\par In Example 4.2.2.1.2, an error occurs because the edge triggered reset is in the event sensitivity list but there is no corresponding }{\b\cf1\cgrid0 if}{\cf1\cgrid0 statement.
\par
\par }{\i\cf1\cgrid0 Example 4.2.2.1.2}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK or }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 RESET)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = IN;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0
\par }\pard\plain \s18\nowidctlpar\adjustright \fs20\cf1 {In Example 4.2.2.1.3, no syntax error occurs, but the logic is incorrect because an active low CLEAR is inferred in the event sensitivity list, but the logic defines an active high CLEAR.
\par }\pard\plain \nowidctlpar\adjustright \fs20\cgrid {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.2.2.1.3}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK or }{\b\cf1\cgrid0 negedge}{\cf1\cgrid0 CLEAR)
\par }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (CLEAR)//This term should be inverted (~CLEAR) to match the sense of the event sensitivity list.
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = 0;
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 else
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par
\par In Example 4.2.2.1.4, an error occurs because more than three event-triggered variables are in the event sensitivity list.
\par
\par }\pard \nowidctlpar\adjustright {\i\cf1\cgrid0 Example 4.2.2.1.4}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK or }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLEAR or }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 SET or }{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 RESET)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (RESET)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = DATA;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 else if}{\cf1\cgrid0 (SET)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = -1;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 else if}{\cf1\cgrid0 (CLEAR)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = 0;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 else
\par }{\cf1\cgrid0 \tab OUT = IN;
\par \'85
\par
\par In Example 4.2.2.1.5, an error occurs because nested event sensitivity lists are not allowed. A synchronous }{\b\cf1\cgrid0 always}{\cf1\cgrid0 block can contain only one synchronous event sensitivity list.
\par
\par }{\i\cf1\cgrid0 Example 4.2.2.1.5}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK)
\par \tab }{\b\cf1\cgrid0 begin
\par }{\cf1\cgrid0 \tab OUT = 0;
\par \tab }{\b\cf1\cgrid0 @}{\cf1\cgrid0 (}{\b\cf1\cgrid0 posedge}{\cf1\cgrid0 CLOCK);
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab OUT = 1;
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0 \tab }{\b\cf1\cgrid0 end
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 4.3 Modeling Level-Sensitive Storage Device Based Hardware Elements (Latches)
\par }{\cf1\cgrid0 Verilog assumes that a variable not explicitly assigned holds its previous value. The hardware synthesized to hold a value after an assertion condition is removed is a latch. Latches wil
l be inferred by incomplete non-synchronous assignments. An assignment shall be }{\i\cf1\cgrid0 complete }{\cf1\cgrid0 if and only if either of the following is true:
\par a) It is unconditional
\par b) It is conditional and a branch exists for every possible value of the selector, and each branch computes a value independent of the previous value of the target of the assignment. Any assignment that is not complete is called an }{\i\cf1\cgrid0
incomplete }{\cf1\cgrid0 assignment. Since a level-sensitive storage device passes the data to the output when the enable is active, the data variables shall be present in the event sensitivity list of the }{\b\cf1\cgrid0 always }{\cf1\cgrid0
statement modeling the level-sensitive storage device.
\par If an assignment is not }{\i\cf1\cgrid0 complete}{\cf1\cgrid0 ,}{\i\cf1\cgrid0 }{\cf1\cgrid0 unwanted latches may be synthesized.
\par
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 In Example 4.3.1 a level-sensitive storage device (latch) is inferred. If ENABLE is disasserted, Q will hold its value.
\par }\pard \nowidctlpar\adjustright {\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.3.1}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (ENABLE or D)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (ENABLE)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab Q = D;
\par \'85
\par
\par In Example 4.3.2, a latch is not inferred because the assignment to Q is }{\i\cf1\cgrid0 complete}{\cf1\cgrid0 .
\par
\par }\pard \nowidctlpar\adjustright {\i\cf1\cgrid0 Example 4.3.2}{\cf1\cgrid0 :
\par }{\b\cf1\cgrid0 always @}{\cf1\cgrid0 (ENABLE or D)
\par \tab }{\b\cf1\cgrid0 if}{\cf1\cgrid0 (ENABLE)
\par }\pard \nowidctlpar\outlinelevel0\adjustright {\cf1\cgrid0 \tab Q = D;
\par \tab }{\b\cf1\cgrid0 else}{\cf1\cgrid0 Q = z;
\par \'85
\par
\par
\par }{\b\cf1\cgrid0 4.4 Other Semantic Rules.
\par
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 4.4.1}{\cf1\cgrid0 Multiple declarations of the same net or register shall be consistent in both size and type. In addition, the use of the range in the port assignments is optional. If left unspecified as
in Example 4.4.1.2, the port assignment will assume the same size and range of the net type assignment.
\par
\par }{\b\cf1\cgrid0 EDITOR\rquote S NOTE: }{\cf1\cgrid0 The Exemplar compiler accepts the following. I can\rquote t tell from reading 1364 if it specifically forbids the inference of the port range. Regardless of 1364, I\rquote
d like to save the designers some unnecessary typing, if possible.
\par
\par }{\i\cf1\cgrid0 Example 4.4.1.1:}{\cf1\cgrid0
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 [2:0] out;\tab // Range is optional for port assignments.
\par \'85
\par
\par }{\i\cf1\cgrid0 Example 4.4.1.2:}{\cf1\cgrid0
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 out;\tab // This form is also acceptable.
\par \tab }{\b\cf1\cgrid0 wire}{\cf1\cgrid0 }{\fs18\cf1\cgrid0 [}{\cf1\cgrid0 2:0] out;\tab // The module port will infer this range.
\par \'85
\par
\par }{\i\cf1\cgrid0 Example 4.4.1.3:
\par }{\cf1\cgrid0 \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 [2:0] out;
\par \tab }{\b\cf1\cgrid0 wire}{\cf1\cgrid0 [2:1] out; // Not supported because the vector ranges do not match.
\par
\par }{\b\cf1\cgrid0 4.4.2}{\cf1\cgrid0 Global references may not cross module boundaries. Variables must be declared in a port list before being used in lower level structures (lower level modules, functions, tasks, or UDPs).
\par
\par In Example 4.4.2.1, an error occurs because an upward hierarchical reference is not supported.
\par
\par }{\i\cf1\cgrid0 Example 4.4.2.1:}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 top(IN, OUT);
\par \tab }{\b\cf1\cgrid0 input}{\cf1\cgrid0 IN;
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 OUT;
\par \tab bot INST();
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bot;
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 top.OUT = top.IN; // Not supported because global reference crosses higher level module boundary.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par In Example 4.4.2.2, the code compiles without error because local references are supported.
\par }{\i\cf1\cgrid0 Example 4.4.2.2:}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 top(IN, OUT);
\par \tab }{\b\cf1\cgrid0 input}{\cf1\cgrid0 IN;
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 OUT;
\par \tab bot INST(IN, OUT);
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bot (bot_input, bot_output);
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 bot_output = bot_input; // Supported through port list assignment.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 EDITOR\rquote S NOTE: }{\cf1\cgrid0 Shalom Bresticker asks if support for the following is necessary. One of the great things about Verilog simulation is that all signals in the design are \lquote visible\rquote
from the top level. Having this capability for wiring up top-level test points would be great. I don\rquote t see why this would be a problem for the synthesizer as long as we\rquote
re allowing only pin assignment and not allowing dumb things like creating logic across module boundaries. It is such a pain to hook up test signals buried in the hierarchy, particularly when multiple instances of a module are used.
\par
\par In Example 4.4.2.3, the code compiles without error because downward connection across module boundaries is supported.
\par }{\i\cf1\cgrid0 Example 4.4.2.3:}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 top(IN, OUT, TEST);
\par \tab }{\b\cf1\cgrid0 input}{\cf1\cgrid0 IN;
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 OUT;
\par \tab bot INST(IN, OUT);
\par \tab TEST\tab =\tab INST.bot_output;\tab // Downward connection across module
\par }\pard \fi720\li2880\nowidctlpar\adjustright {\cf1\cgrid0 // boundaries are supported.
\par }\pard \nowidctlpar\adjustright {\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bot (bot_input, bot_output);
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 bot_output = bot_input; // Supported through port list assignment.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0
\par }{\cf1\cgrid0 In Example 4.4.2.4, an error occurs because downward references across module boundaries can be used for interconnection purposes only.
\par }{\b\cf1\cgrid0
\par }{\i\cf1\cgrid0 Example 4.4.2.4:}{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 top(IN, OUT, TEST1, TEST2);
\par \tab }{\b\cf1\cgrid0 input}{\cf1\cgrid0 IN, TEST1;
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 OUT, TEST2;
\par \tab bot INST(IN, OUT);
\par \tab TEST2\tab =\tab TEST1 & INST.bot_output; // Not supported.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bot (bot_input, bot_output);
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 bot_output = bot_input; \tab // Supported through port list assignment.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par
\par }{\b\cf1\cgrid0 4.4.3}{\cf1\cgrid0 All instance inputs should be connected}{\f16\cgrid0 .
\par
\par }{\i\cf1\cgrid0 Example 4.4.3.1:
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 top(IN, OUT);
\par \tab }{\b\cf1\cgrid0 input}{\cf1\cgrid0 IN;
\par \tab }{\b\cf1\cgrid0 output}{\cf1\cgrid0 OUT;
\par \tab bot INST(1'b0, OUT);\tab // Unused input connected.
\par }{\b\cf1\cgrid0 endmodule
\par }{\cf1\cgrid0
\par }{\b\cf1\cgrid0 module}{\cf1\cgrid0 bot (IN, OUT);
\par }{\b\cf1\cgrid0 assign}{\cf1\cgrid0 bot_output = bot_input;
\par }{\b\cf1\cgrid0 endmodule
\par }{\cgrid0
\par }}
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