Re: Verilog RTL Synthesis, Semantics Section 4.

Ken Coffman (kcoffman@sos.net)
Wed, 09 Sep 1998 06:21:22 -0700

Please ignore the filenames, its 1364dot1 of course.
Electrical insulation is one of my favorite subjects,
I had to get it in there somewhere.
Next time I'll change the filenames to something more
appropriate like PleaseIgnoreTitle.doc or
ImABozoWhoCantSeemToFigureOutWhichSpecImWorkingOn.RTF
- Regards.

At 11:04 AM 9/8/98 -0400, you wrote:
>Ken:
>
>> Here's the latest revision of P1364.1, section 4. I think we're making
>> progress.
>
>Shouldn't these be "1364.1rev.xxx" and not "1064rev.xxx"?
>
>IEEE 1064 is a withdrawn spec for "Multifactor Stress Functional Testing of
>Electrical Insulation Systems" which appears to have little to do with
>writing Verilog code.
>
>NAME: David W. Bishop INTERNET: dbishop@vhdl.org ( \ )
>US MAIL: Hilton NY 14468-9101 A Long time ago, \__\/
>PHYSICAL: 43:17:17N 77:47:37W 281' In a Galaxy far, far away... | |
>For Supernova info: http://www.ggw.org/asras/supernova.html | |
>For VHDL/Synthesis info: http://www.vhdl.org/siwg _/___\_
>All standard disclaimers apply. [_______]
>
>
>