Subject: RE: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr 5, '02
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Mon Apr 08 2002 - 06:41:14 PDT
MEETING MINUTES: Telecon April 5, 2002.
Attendees:
Muzaffer Kal
Jenjen Tiao
Cliff Cummings
Ben Cohen
J. Bhasker
1. Discussed the test_port attribute. Agreed on the following:
- New ports added due to test_port attribute to be added at end of port list. The order of
the test_ports itself is not specified by the standard.
- The naming convention for test_ports is not specified by the standard.
Rationale: Vendors already may have their own naming conventions for naming newly created items.
So may be hard to agree on one. Naming convention does not affect RTL model portability. Only
effects netlists, and thats ok.
- Accepted Ben's note: "The appearance or omission of a test_port as a result of optimization may
be reported by the synthesis tool".
- Accepted Ben's note: Only a single bit or a single-dimen array can be attributed with test_port.
- Accepted Ben's note: If a test_port object is optimized out, that object shall not be mapped onto
a port. Add note that says user may use the keep attribute with test_port attribute if user does not
want the object optimized out.
- Agreed to add Ben's example on test_port attribute to draft.
2. "Assigning X" issue posted by MKal: Muzaffer mentioned that he had posted based on an old draft and
that there was no longer an issue.
3. "1364.1 v2.1 draft comments" posted by BCohen:
- 5.7: agreed to Ben's proposal: replace "combinational logic" by "latch or register logic".
- pg 21: agreed to Ben's proposal on keep attribute.
- pg 23: There was no issue here as rst is synchronous.
- pg 76: Specify section is already marked ignored. No change to be made.
4. Syntax of synthesis attribute: accepted as proposed by Ben, modified by Daryl.
5. JenJen Tiao, MKal, and others noted some varying fonts in the syntax chapter. Cliff volunteered
to take a crack at making it consistent. Bhasker to send chapter to Cliff. Cliff to send back
changes to Bhasker by April 15.
6. All above changes will be made in draft 2.2. This is the draft that will be sent out for ballot.
The draft will be sent out on Apr 20 to IEEE.
7. IEEE ballot group has been formed and approved. Cliff agreed to call people he knows on the ballot list
to remind to vote.
8. Bhasker briefly talked about the IEEE process. Today was the last regular WG meeting. Bhasker to
post IEEE standardization process status regularly. Next WG meeting will most probably occur after
all the ballot responses are back (sometime in June).
- bhasker
-----Original Message-----
From: Jayaram Bhasker
Sent: Friday, March 29, 2002 10:54 AM
To: vlog-synth@eda.org
Subject: Verilog RTL Synthesis Interoperability WG meeting: Telecon Apr
5, '02
The next Verilog RTL Synthesis Interoperability WG meeting is scheduled as
a teleconference for Friday, April 5, 2002.
The call details are:
CALL DATE: APR-05-2002 (Friday)
CALL TIME: 12:00 PM EASTERN TIME
DURATION: 1 hr 30 min
USA Toll Free Number: 888-396-9971
USA Toll Number: +1-712-271-0003
PASSCODE: 39996
LEADER: Mr Jayaram Bhasker
Agenda:
1. IEEE standardization process update.
2. Discussion on test_port attribute.
3. Any other issues posted on review of draft 2.1.
4. This would most probably be our last regular Working Group meeting.
Regards,
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
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