Subject: Re: section 5.6 ROM // Question
From: VhdlCohen@aol.com
Date: Fri Apr 05 2002 - 15:51:35 PST
Same comment for the RAM.
Change from:
"A RAM shall be modeled using a Verilog memory (a two-dimensional reg array)
that has the attribute
ram_block associated with it."
Change to:
"A RAM shall be modeled using a Verilog memory (a two-dimensional reg array)
and may have the attribute
ram_block associated with it."
Rationale: Current vendors will implement the ram without the attribute //
tool dependent
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Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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