Subject: Re: recursive instantiations of modules
From: M Ciletti (eagle64@email.msn.com)
Date: Sun Mar 10 2002 - 14:30:22 PST
The formal syntax (see Annex A, p. 594 of the LRM) states the following:
module_declaration ::=
module_keyword module_identifier [list_of_ports]; {module_item} endmodule
module_item_declaration ::=
parameter_declaration
| input_declaration
| output_declaration
| inout_declaration
| net_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| task_declaration
| function_declaration
Module declarations are not among the allowed module items.
Mike Ciletti
----- Original Message -----
From: Michael J. S. Smith (PacBell)
To: Shalom Bresticker ; M Ciletti
Cc: VhdlCohen@aol.com ; vlog-synth@eda.org
Sent: Sunday, March 10, 2002 3:23 PM
Subject: Re: recursive instantiations of modules
First, on recursion applied to modules.
I don't believe this issue is covered explicitly in the formal syntax definition (BNF) of Verilog 1995. However, it seems to me that the BNF formal syntax does allow module recursion (since there is no meaning in a name in the BNF and syntax) and would be the duty of the grammar description in the main body to prevent it. As far as I can see it's not covered in the grammar definitions of Chapter 12 of the 1995 LRM (there's mention of nesting but no mention of recursion).
See http://www.deepchip.com/posts/0254.html for an example of the use of recursion in XOR trees.
See http://citeseer.nj.nec.com/30053.html and http://citeseer.nj.nec.com/cache/papers/cs/408/http:zSzzSztech-www.informatik.uni-hamburg.dezSzvhdlzSzmodelszSzrecursivezSztech-report.pdf/recursive-and-repetitive-hardware.pdf for a paper on the use of HDL recursion.
(See also several other news articles pointed to by Google(recursion Verilog).
(and by the way, an indirect link from the Ashendon paper, http://citeseer.nj.nec.com/cache/papers/cs/11764/http:zSzzSzwww.cl.cam.ac.ukzSzuserszSzmvi20zSzhandelzSzdesc.pdf/verilog-expression-evaluation.pdf is an interesting read for this group too, pointing out several non-normative Verilog issues.)
I've looked briefly at Verilog 2001, but I don't have the original source document in electronic form, which makes it harder to find things for sure. I look forward to seeing the answer to the question on module recursion from the folks involved with the 2001 document.
Recursive tasks and functions, which were also part of the original question, are much better understood I think. I'll leave those.
Aloha
Mike Smith
University of Hawaii
CTO, iReady
----- Original Message -----
From: Shalom Bresticker
To: M Ciletti
Cc: VhdlCohen@aol.com ; vlog-synth@eda.org
Sent: Sunday, March 10, 2002 7:32 AM
Subject: Re: recursive instantiations of modules
Where?
M Ciletti wrote:
FYI - The formal syntax of Verilog precludes recursive instantiation of modules, regardless of what tools might do before they choke on attempted nonsense. Mike Ciletti
--
Shalom Bresticker Shalom.Bresticker@motorola.com
Principal Staff Engineer Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
POB 2208, Herzlia 46120, ISRAEL Cell: +972 50 441478
This archive was generated by hypermail 2b28 : Sun Mar 10 2002 - 14:40:44 PST