Subject: Re: recursive instantiations of modules
From: M Ciletti (eagle64@email.msn.com)
Date: Sun Mar 10 2002 - 14:28:38 PST
The formal syntax (see Annex A, p. 594 of the LRM) states the following:
module_declaration ::=
module_keyword module_identifier [list_of_ports]; {module_item} endmodule
module_item_declaration ::=
parameter_declaration
| input_declaration
| output_declaration
| inout_declaration
| net_declaration
| reg_declaration
| integer_declaration
| real_declaration
| time_declaration
| realtime_declaration
| event_declaration
| task_declaration
| function_declaration
Module declarations are not among the allowed module items.
Mike Ciletti
----- Original Message -----
From: Shalom Bresticker
To: M Ciletti
Cc: VhdlCohen@aol.com ; vlog-synth@server.eda.org
Sent: Sunday, March 10, 2002 8:32 AM
Subject: Re: recursive instantiations of modules
Where?
M Ciletti wrote:
FYI - The formal syntax of Verilog precludes recursive instantiation of modules, regardless of what tools might do before they choke on attempted nonsense. Mike Ciletti
--
Shalom Bresticker Shalom.Bresticker@motorola.com
Principal Staff Engineer Tel: +972 9 9522268
Motorola Semiconductor Israel, Ltd. Fax: +972 9 9522890
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