Subject: RE: recursive instantiations of modules
From: Muzaffer Kal (muzaffer@dspia.com)
Date: Sun Mar 10 2002 - 15:15:45 PST
But isn't there a difference between module declaration and module
instantiation ? To me it seems that recursive module instantiation is still
technically possible.
-----Original Message-----
From: owner-vlog-synth@server.eda.org
[mailto:owner-vlog-synth@server.eda.org]On Behalf Of M Ciletti
Sent: Sunday, March 10, 2002 2:29 PM
To: Shalom Bresticker
Cc: VhdlCohen@aol.com; vlog-synth@server.eda.org
Subject: Re: recursive instantiations of modules
The formal syntax (see Annex A, p. 594 of the LRM) states the following:
...
Module declarations are not among the allowed module items.
Mike Ciletti
----- Original Message -----
From: Shalom Bresticker
To: M Ciletti
Cc: VhdlCohen@aol.com ; vlog-synth@server.eda.org
Sent: Sunday, March 10, 2002 8:32 AM
Subject: Re: recursive instantiations of modules
Where?
M Ciletti wrote:
FYI - The formal syntax of Verilog precludes recursive instantiation
of modules, regardless of what tools might do before they choke on attempted
nonsense. Mike Ciletti
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