Re: [vlog-synth] Signed Multiplier generation

Shiladitya,

The way I do it, is to simply manually sign-extend all
my arguments to the resulting size before doing
the operation i.e.

input [ 15 : 0 ] a;
input [ 15 : 0 ] b;
output [ 31 : 0 ] product;

wire [ 31 : 0 ] a_sign_extended = { { 16 { a[ 15 ] } }, a };
wire [ 31 : 0 ] b_sign_extended = { { 16 { b[ 15 ] } }, b };
wire [ 31 : 0 ] product = a_sign_extended * b_sign_extended;

Scratch out a few examples with smaller
sizes to convince yourself this works.
Even works when a, b have unmatched sizes.

dc_shell seems to produce acceptable (area,timing) with this.

This mostly works, in general, with other math
operations too.

Regards,

Mark

On Mon, Mar 29, 2004 at 12:52:05PM +0530, Biswas, Shiladitya wrote:
> Hi
>
> How can I generate a signed multiplier in Verilog? Suppose I want to
> generate a multiplier which takes two signed 16 bit inputs and produces
> a 32 bit output what code should I write?
>
> Thanks
>

-- 
Mark Curry           
Texas Instruments Broadband Communications Group