>The way I do it, is to simply manually sign-extend all
>my arguments to the resulting size before doing
>the operation i.e.
With Verilog-2001, you can take advantage of the signed arithmetic
extensions to do this sign-extension for you (assuming the synthesis
tools handle it properly).
As Mark says, that is really the only difference between signed and
unsigned multiplication. Verilog multiplies are not actually defined
as "widening multiplies", so there is no actual difference between the
operations for a signed and unsigned multiply. The apparent "widening
multiply" you get by assigning the result to a wide enough output is
actually done by extending the inputs to the result size and then doing
the multiply. It is the zero vs. sign-extension of the inputs that
determines whether the multiply acts like an unsigned or signed operation.
>This mostly works, in general, with other math
>operations too.
The only actual signed operations that come to mind are division, modulo,
right-shift, and magnitude compares. With other operations, it is just
the zero vs sign-extension of the operands that makes the difference.
Steven Sharp
sharp@cadence.com
Received on Mon Mar 29 11:39:10 2004
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