[vlog-synth] Signed Multiplier generation

Hi

How can I generate a signed multiplier in Verilog? Suppose I want to
generate a multiplier which takes two signed 16 bit inputs and produces
a 32 bit output what code should I write?

Thanks

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Shiladitya Biswas "The woods are
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Received on Sun Mar 28 23:22:15 2004