0. General: Please remember that an official standards document must be precise.
All terms must be well-defined. All sentences must be clear. There's no room
for writing "approximately", saying that "everyone will understand".
1. Section 4.1: The second paragraph uses the term "level-triggered signals".
The term is undefined. That's not just nitpicking, I honestly do not
understand what the intended meaning is. And if I don't, there will be others also.
The only meaning I can think of is a short way of saying "the output of a
level-sensitive storage device", but that meaning does not make sense in this context.
2. After the examples appears the sentence, "The minimum set of signals
must be specified". What is the definition of "the minimum set of signals" ?
What is "must": "only" or "at least" ? And should it be "shall" or "should" ?
3. The sentence "In the following example, both IN1 and IN2 fail to satisfy the
requirements for input signals" is not clear. What are the "requirements for
input signals" ?
4. Since the example is of procedural CONTINUOUS assignments, it should be:
always @(SEL or IN1) // Legal, even though IN1 is not required
if (SEL)
assign OUT = IN1;
else
assign OUT = IN2;
5. The following is garbled:
"The same register cannot be assigned in both procedural-continuous and non procedural-continuous manner.
Example:
always @(IN1 or IN2 or SEL)
begin
OUT = IN1; // procedural assignment
if (SEL)
OUT = 2; // Non-blocking assignment. Mixing blocking and non-blocking assignments in and always block is not supported.
end
"
It mixes up procedural continuous/non-continuous assignments and blocking/non-blocking assignments.
Also IN2 should not be in the sensitivity list.
6. Section 4.2.2: "All ... shall be modeled by sequential statements that assign to a variable".
Not clear. What is a "sequential statement"? Considering the following sentence, maybe the
intention is "All .. shall be modeled by synchronous assignments to a variable. A synchronous
assignment is ..."
7. "A synchronous assignment shall be defined as an assignment under the control of a clock":
Improper use of "shall". Instead of "shall be defined as", how about "is" ?
And if it's a definition, maybe it should be in Section 2 ?
Change "assignment" to "procedural assignment" ?
8. Section 4.2.3: Since 4.2 is edge-sensitive and this is level-sensitive, this
should be 4.3.
9. The first sentence, "Level-sensitive storage devices shall be inferred ..."
is unclear. What is a "non-synchronous assignment" ? If a "synchronous assignment"
"is an assignment under the control of a clock", well then, if I write
always @ (CLK)
if (CLK)
B = A ;
that certainly is under the control of a clock, so it's not a level-sensitive storage device ?
For that matter, what is the defintion of a clock ?
10. The sentence is almost self-referential: what is a "level-sensitive manner" ? It is undefined.
11. 4.3 Tasks and Functions, of course, has to be re-written.
12. 4.4.1: "The use of the range in the port assignments is optional."
NO! This is illegal in Verilog (1364)!
13. Is it necessary to support the following?:
"Example:
module top(IN, OUT, TEST);
input IN;
output OUT;
bot INST(IN, OUT);
TEST = INST.bot_output; // Downward connections across module are supported.
endmodule
module bot (bot_input, bot_output);
assign bot_output = bot_input; // Supported through port list assignment.
endmodule"
Sincerely,
Shalom Bresticker
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Shalom Bresticker email: shalom@msil.sps.mot.com
Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522444
http://www.motorola-semi.co.il/
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