As a result of today's conference call meeting we have decided
to go ahead with standardizing IEEE 1364.1 with respect to
the current Verilog standard IEEE 1364-1995. We will add any
pertinent footnotes for the time being relating to what we might
like to have in the standard if we are able to incorporate
changes into IEEE 1364-1995, which may, or may not, be
updated next year. The plan is still to standardize IEEE 1364.1
by the end of this year if possible.
Regarding pragmas, we will therefore stick with:
// rtl_synthesis off
// rtl_synthesis on
and have a footnote suggesting something like:
`translate off
`translate on
or
`synthesis_translate off
`synthesis_translate on
Need you comments
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any particular synthesis tool shall implement fixed functionality.
However, from a practical users point of view it is not possible, for
example, to tell a synthesis tool that a certain signal shall be used as
the enable to a flip-flop, or that an if statement shall map to an 8-1
multiplexor.
If we start adding a lot of new implementation specific pragmas
we are specifying how the synthesis tool shall work. For example,
one synthesis tool could implement an 8-1 multiplexer faster
in gate level primitives, rather than being told specifically to map
to am 8-1 multiplexer.
Any comments on this is appreciated.
Doug Smith
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Douglas J. Smith
VeriBest, Inc.
email: djsmith@veribest.com
phone: (256) 730 - 8808
fax: (256) 730 - 8344
http://www.veribest.com
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