As an initial proposal, I would like to dedicate a `namespace
to synthesis related compiler directives. I would expect the
standard to give the synthesis working group some room to
decide which directives to implement.
I propose that we create directives of the form
`synthesis_<keyword> [arguments]
As an example we can include the obvious:
`synthesis_translate on
`synthesis_translate off
Most importantly, this will:
1) Allow the synthesis working goup to use compiler directives
(which is the preferred way to direct the compiler versus
magic comments)
2) Does not require the Verilog standard to specify the exact
set of synthesis directives.
Regards,
Stefen
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Stefen Boyd
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