Subject: Re: Verilog Synthesis Interoperability Working Group: Agenda for July 6, '01
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Thu Jul 05 2001 - 09:01:02 PDT
REMINDER! REMINDER! REMINDER!
> X-Sender: jbhasker@at-mailhost
> Date: Tue, 19 Jun 2001 16:03:23 -0400
> To: vlog-synth@eda.org
> From: "J. Bhasker" <jbhasker>
> Subject: Re: Verilog Synthesis Interoperability Working Group: Agenda for
July 6, '01
> Mime-Version: 1.0
> X-Received: By mailgate.Cadence.COM as NAA13754 at Tue Jun 19 13:49:57 2001
> X-Keywords:
>
> Here are the callin details:
>
> >From US, call 877.601.3551
> >From outside US, call +1-712-271-3620
> Passcode: 43657 (it is NOT 007007)
>
> - bhasker
>
> At 09:09 AM 5/30/01 -0400, J. Bhasker wrote:
> >The next Verilog Synthesis Interoperability Working Group phone
> >conference is scheduled for FRIDAY, JULY 06 from 12:00pm to 1:30pm
> >EASTERN STANDARD TIME.
> >
> >Call <info will be sent later>,
> >and enter the passcode 007007.
> >
> >Agenda:
> >
> >1. To discuss the synthesizability of the following new features
> > of Verilog-2000:
> > - generate block
> > - multidimensional arrays
> > - bit and part-select with arrays
> > - Enhanced file i/o
> > (others at future meetings)
> >
> >2. Looking for a leader to help out with the documentation.
> >
> >Future telecon dates: Aug 10, Sept 14
> >
> >Regards,
> >
> >- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
> > Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
> > Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
> >
> >
J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com
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