Re: recursive instantiations of modules

Subject: Re: recursive instantiations of modules
From: M Ciletti (eagle64@email.msn.com)
Date: Mon Mar 11 2002 - 05:46:38 PST

I agree. The wording could have been clearer, just to emphasize that only previously declared modules may be instantiated inside the declaration of a module.

Mike
  ----- Original Message -----
  From: Shalom Bresticker
  To: Muzaffer Kal
  Cc: M Ciletti ; vlog-synth@server.eda.org ; btf@boyd.com
  Sent: Monday, March 11, 2002 2:25 AM
  Subject: Re: recursive instantiations of modules

  You are correct about the difference between module declaration and instantiation.
  The closest the standard comes to talking about this is the statment that a module may contain instantiations of "other modules", which you might want to read as implicitly forbidding self-instantiation.

  But in fact, recursive instantiation was never really discussed.

  It came up once in http://boyd.com/1364_btf/archive/btf_2000/1123.html ,
  but the issue was never resolved.

  I guess that is an open issue.

  Shalom
    

  Muzaffer Kal wrote:

    But isn't there a difference between module declaration and module instantiation ? To me it seems that recursive module instantiation is still technically possible.
      -----Original Message-----
      From: owner-vlog-synth@server.eda.org [mailto:owner-vlog-synth@server.eda.org]On Behalf Of M Ciletti
      Sent: Sunday, March 10, 2002 2:29 PM
      To: Shalom Bresticker
      Cc: VhdlCohen@aol.com; vlog-synth@server.eda.org
      Subject: Re: recursive instantiations of modules
      The formal syntax (see Annex A, p. 594 of the LRM) states the following:...Module declarations are not among the allowed module items.
      Mike Ciletti

        ----- Original Message -----
        From:Shalom Bresticker
        To: M Ciletti
        Cc: VhdlCohen@aol.com ; vlog-synth@server.eda.org
        Sent: Sunday, March 10, 2002 8:32 AM
        Subject: Re: recursive instantiations of modules
         Where?
        M Ciletti wrote:

          FYI - The formal syntax of Verilog precludes recursive instantiation of modules, regardless of what tools might do before they choke on attempted nonsense. Mike Ciletti 

-- 
Shalom Bresticker                           Shalom.Bresticker@motorola.com
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