Subject: Re: recursive instantiations of modules
From: M Ciletti (eagle64@email.msn.com)
Date: Fri Mar 08 2002 - 19:10:43 PST
FYI - The formal syntax of Verilog precludes recursive instantiation of modules, regardless of what tools might do before they choke on attempted nonsense.
Mike Ciletti
----- Original Message -----
From: VhdlCohen@aol.com
To: vlog-synth@server.eda.org
Sent: Friday, March 08, 2002 3:42 PM
Subject: recursive instantiations of modules
An interesting question came up:
Do we allow ib Verilog ('95 or '01) recursive instantiation of modules? Below is an example:
module my_not(out, in);
input in;
output out;
my_not inst(out, in);
endmodule
module bin2gray (gray, bin);
parameter SIZE = 4;
output [SIZE-1:0] gray;
input [SIZE-1:0] bin;
assign gray = (bin>>1) ^ bin;
my_not gray_1(gray, bin);
endmodule
for the record, compilation in NC-Sim and and ModelSim yielded the following:
%ncvlog testrec.v
ncvlog: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
%ncelab bin2gray
ncelab: v03.30.(p001): (c) Copyright 1995 - 2001 Cadence Design Systems, Inc.
ncelab: *W,CUSRCH: Resolved module/udp 'my_not' at 'gray_1' to 'work_lib.my_not:module' through a global search of all libraries.
ncelab: *E,CUTODP: maximum design hierarchy component instance depth (64) exceeded.
Module instantiation: bin2gray.gray_1.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst.inst
%
%vlog testrec.v
Model Technology ModelSim SE vlog 5.5a Compiler 2001.04 Apr 5 2001
-- Compiling module my_not
-- Compiling module bin2gray
Top level modules:
bin2gray
Simulation in ModelSim crashed, and exited after elaboration.
In the context of generates sometimes it may result in limited recursion
and create hardware. Someone might argue about this and I
dont have anything to show why this would be illegal usage.
From a hardware point of view I am failing to visualize how a module can instantiate itself, when it was not completely defined.
Recursive functions (e.g., factorial), the function terminates when the actual is a 1.
Factorial (x) function calls factorial(x-1), but stops when (x-1) = 1. In hardware though, I would have difficulty visualizing this because:
1. There is no STOP. I guess you could instantiate a module where last instance is itself with no components ?
(ambiguous)
2. Drivers. Multiple drivers would result.
Bottom line, I don't know if Vlog2001 would allow this (I don't think so, but even if it did, the whole thing does NOT make sense and should be discouraged as a design mechanism.
Recursive functions: OK.
Recursive modules: NO I challenge anyone to try to explain what that means!
Is there anyone out there who has seen or applied this module recursion before?
I am amazed how Verilog would compile almost anything!
Comments?
Thanks,
Ben
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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