Subject: Re: Assigning / testing different sizes -- shouldn't we restrict the use?
From: VhdlCohen@aol.com
Date: Thu Aug 09 2001 - 09:41:45 PDT
<<Verilog lint checkers already flag such cases. A good synthesis tool also
generates warnings for such.>>
For the record, SYnopsys Design Compiler did not give any warning either ...
Perhaps becuase its OK in Verilog to assign X bits onto an N bit signal.
Ben
---- dc_shell-t> analyze -format verilog /home/vpjc/bens.v Loading db file '/home/synopsys_00.11/libraries/syn/standard.sldb' Loading db file '/home/synopsys_00.11/libraries/syn/gtech.db' Reading in the Synopsys verilog primitives. /home/vpjc/bens.v: 1 dc_shell-t> elaborate ff_resetInferred memory devices in process in routine ff_reset line 9 in file '/home/vpjc/bens.v'. ============================================================================== = | Register Name | Type | Width | Bus | MB | AR | AS | SR | SS | ST | ============================================================================== = | q_reg | Flip-flop | 1 | - | - | N | N | N | N | N | ============================================================================== =
Current design is now 'ff_reset' 1 dc_shell-t>
module ff_reset (q, d, d1, clk, ldenb, ldenb1, rst); output q; // output <<< Should have been "output [3:0] q;" input [3:0] d; // data input input [1:0] d1; // data1 input input clk; // clock input rst; // reset, active hi input ldenb, ldenb1; // load enable reg q; // FF output << Should have been reg [3:0] q; always @(posedge clk or posedge rst) begin if (rst) q <= 1'b0; else if (ldenb) q <= {d[3:2], ~d[1:0]}; else if (ldenb1) q <= d1; end endmodule
Synplicity Verilog Compiler, version 6.2.0, Build 097R, built Apr 16 2001 Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved
@I::"c:\vhdl_stuff\__dsgn\ff_reset2.v" Verilog syntax check successful! Selecting top level module ff_reset Synthesizing module ff_reset @END Process took 1.04 seconds realtime, 1.09 seconds cputime Synplicity Altera Technology Mapper, version 6.2.0, Build 096R, built Apr 13 2001 Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved Created 1 cliques with a total of 2 instances along critical paths Created 1 cliques with a total of 2 instances along critical paths --- Xilinx WebPack 3.2 Starting Verilog synthesis.
Analyzing top module <ff_reset>. Module <ff_reset> is correct for synthesis.
Synthesizing Unit <ff_reset>. Extracting 1-bit register for signal <q>. Extracting 1-bit 2-to-1 multiplexer for internal node. WARNING : (HDL__0002). Input <d1<1>> is never used. WARNING : (HDL__0002). Input <d<3>> is never used. WARNING : (HDL__0002). Input <d<2>> is never used. WARNING : (HDL__0002). Input <d<1>> is never used. Summary: inferred 1 D-type flip-flop(s). inferred 1 Multiplexer(s). Unit <ff_reset> synthesized.
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--- n a message dated 8/6/01 2:56:43 PM Pacific Daylight Time, VhdlCohen@aol.com writes:
> Below is code with a 4-bit input port and a 1-bit output port. > Testing the 4-bit input against a 1-bit value or a value greater thatn > 4-bits seems OK in synthesis. > Also writing a 4-bit value onto a 1-bit port seems also OK in synthesis. > What does that mean in hardware? Obvioulsy, this is an error, and similar > code would NOT compile in VHDL. > Question to this group: Shouldn't we restrict such erroneous use of Verilog > for synthesis (i.e., make it an error)? > Incidentally, code as shown below is difficult to automatically translate > into VHDL (thinking of automatic tools), and makes no hardware sense. > > <<Verilog lint checkers already flag such cases. A good synthesis tool also > generates warnings for such.>> > There is NO requirement in our spec that "lint checkers must be used prior > to > synthesis". > If we do that, then we have to define what a lint checker does. Also, I > tried 2 synthesis tools (Synplify and Xilinx WebPack, and both of them > accepted the verilog code with NO complaints or warnings, and wired ain[0] > as > the vector. > > For integers, sometimes the logic does not make sense. For example: > if (ain > 35) -- This is always false because ain max value is 15!!! > This is also the case (for integers only) in VHDL. > > module testlog (ain, clk, cout/*AUTOARG*/ ) ; > input [3:0] ain; > input clk; > output cout; > > reg cout; > > always @ (posedge(clk)) begin > if (ain == 1'b0) > cout <= ~ain; > else if (ain > 35) -- This is always false because ain max value is > 15!!! > cout <= ^ain; > else > cout <= ain; > end > > endmodule > > > Below is a VHDL model that is equivalent to the Verilog code. > Compilation with ModelSim and ncvhdl are alos included. > Ben > --- > library ieee; > use ieee.std_logic_1164.all; > use ieee.NUMERIC_UNSIGNED.all; > entity testlog is > port (ain : in std_logic_vector(3 downto 0); -- 4 bits > clk : in std_logic; > cout : out std_logic) ; -- 1 bit > end entity; > > architecture beh of testlog is > begin > process (clk) > variable tmp : std_logic; > begin > if (clk'event and clk = '1') then > if (ain = '0') then -- if (ain == 1'b0) > cout <= not ain; -- 1bit assigned the NOT of 4 bit input vector > //ERROR > elsif (TO_INTEGER(ain) > 35) then > tmp := '0'; > for i in ain'range loop > tmp := tmp xor ain(i); > cout <= tmp; -- cout <= ^ain;, -- 1 bit assigned a 1 bit OK here > end loop; -- if ain > 35 > else > cout <= ain; -- cout <= ain; -- 1 bit assigned 4 bits //ERROR > end if; > end if; -- clock edge > end process; > end architecture beh; > > %vcom -93 testlog.vhd > Model Technology ModelSim SE/EE vcom 5.4b Compiler 2000.06 Jun 8 2000 > -- Loading package standard > -- Loading package std_logic_1164 > -- Loading package numeric_std > -- Loading package numeric_unsigned > -- Compiling entity testlog > -- Compiling architecture beh of testlog > ERROR: testlog.vhd(16): No feasible entries for infix op: "=" > ERROR: testlog.vhd(16): Type error resolving infix expression. > ERROR: testlog.vhd(17): Type error resolving prefix expression. > ERROR: testlog.vhd(25): Type error in variable ain. Needed type std_logic. > ERROR: testlog.vhd(29): VHDL Compiler exiting > %ncvhdl -v93 testlog.vhd > ncvhdl: v3.20.(p1): (c) Copyright 1995 - 2000 Cadence Design Systems, Inc. > if (ain = '0') then -- if (ain == 1'b0) > | > ncvhdl_p: *E,OPTYMM (testlog.vhd,16|14): operator argument type mismatch > 87[4.3.3.2] 93[4.3.2.2] [7.2] [10.5]. > cout <= not ain; -- 1bit assigned the NOT of 4 bit input vector > //ERROR > | > ncvhdl_p: *E,EXPTYP (testlog.vhd,17|18): expecting an expression of type > STD_ULOGIC 87[8.3] 93[8.4]. > cout <= ain; -- cout <= ain; -- 1 bit assigned 4 bits //ERROR > | > ncvhdl_p: *E,EXPTYP (testlog.vhd,25|20): expecting an expression of type > STD_ULOGIC 87[8.3] 93[8.4]. > % > > > >
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-------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Component Design by Example ... a Step-by-Step Process Using VHDL with UART as Vehicle", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------
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