Subject: Re: Generate & defparams in Vlog-2001.
From: Stefen Boyd (stefen@boyd.com)
Date: Thu Aug 09 2001 - 09:19:09 PDT
At 12:26 PM 8/9/2001 +0300, Shalom Bresticker wrote:
>Stefen Boyd wrote:
>> > > In this case, since you want to override the value of the parameter in
>> > > only one of the instances,
>> > > you would put the defparam outside of the generate.
>> >
>> >I guess this would be flagged as a syntax error, since
>> >it would be an illegal name in verilog.
>> >
>> >Consider:
>> >
>> >defparam somename[0].myflop.xyz = 1;
>>This is illegal because you can't defparam into the
>>generated scope... as Steven Sharp mentioned.
>Wait a minute.
>
>Steven Sharp (too many "Ste[fv]ens" here ...) was talking about
>a defparam from inside the generate to outside the generate.
>He was not referring to a defparam which is located outside the
>generate and references a parameter which is inside the generate.
>
>By the way, when I read the standard, I understood the meaning to
>allow a defparam from one iteration of the generate loop to another
>iteration,
>and not as Steven Sharp wrote.
>If that was not the intention, it has to be rewritten.
>
oops, I got it turned around... back to the original question:
At 04:00 PM 8/8/2001 -0700, Krishna Garlapati wrote:
>Consider:
>
>defparam somename[0].myflop.xyz = 1;
>
>declared outside the generate block. The reader reads
>'somename', comes across the subscript, '[0]' and flags an
>error since it was expecting a simple_identifier( name ) for
>the defparam. My question was how would the reader know
>that "somename[0].myflop" is the name for an instance in
>the current module. ??
looks like you're going to have to get used to seeing
additional scope before instances (just like with other
declarations inside a named block)... what's new is that
you will have named blocks that create scope for modules
and are indexed.
>> >I definitely agree that defparams are not a good.
>I partly disagree.
>
>I think defparams have a place.
With lots of discipline, defparams can work... but the
vast majority abuse them and make their Verilog unreadable
and unmaintainable...
Stefen
--------------------
Stefen Boyd Boyd Technology, Inc.
stefen@BoydTechInc.com (408)739-BOYD
www.BoydTechInc.com (408)739-1402 (fax)
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