FW: Ballot response document


Subject: FW: Ballot response document
From: Jayaram Bhasker (JBhasker@esilicon.com)
Date: Wed Aug 21 2002 - 08:27:30 PDT


Jenjen:

Thanks for your feedback so far. And yes, do post your comments to the
reflector.

- bhasker

------
J. Bhasker
Chair, Verilog Synthesis Interoperability Working Group
http://www.eda.org/vlog-synth
jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)

-----Original Message-----
From: Jenjen Tiao [mailto:tiao@agere.com]
Sent: Tuesday, August 20, 2002 5:15 PM
To: Jayaram Bhasker
Subject: Re: Ballot response document

Bhasker,

     Please help me put this on the reflector if that's where we should be
responding
to. I am writing you my feedback thus far (I've gone upto issue JL05; page 7
of
the
pdf file) since I don't know if this will be my last time looking at it.
More
to follow
tomorrow if I'm not in labor... :,)

JAE01: the author seems to be saying that the translate_off/_on should be
kept,

explain to him the reasoning behind the WG resolution

SG02: I would like to suggest that all of the example code (whether in part
or
whole)
need to be verified by actually generating the synthesizable code to ensure
the

correctness of the comments and explanation given in the doc. However, since
there are quite a bit through out the entire doc, at least verify the ones
now
that
will be given in response to the ballot.

JG01: explain to the author by stating to him the scope of the standard.

JL05: elaborate a bit more to the author on why the restriction has been
considered
unnecessary.

Jenjen

Jayaram Bhasker wrote:

> WG members:
>
> The ballot response team has completed their work and the ballot response
> document is posted for your feedback on the
> website (http://www.eda.org/vlog-synth, under "Draft Documentation"). This
> document shows the comments made as part
> of the ballot and the changes that will be made to the next revision of
the
> draft.
>
> Please review and provide feedback by Aug 28, 2002.
>
> - bhasker
>
> ------
> J. Bhasker
> Chair, Verilog Synthesis Interoperability Working Group
> http://www.eda.org/vlog-synth
> jbhasker@esilicon.com, 610.439.6831, 610.770.9634(fax)



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