Subject: RE: Initial Blocks fail with Synopsys Tools
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Mon Oct 08 2001 - 11:54:15 PDT
Jim:
One of the things we are considering is the support of constant assignment
statements within an initial statement.
This would be useful, for example, in specifying the contents of a ROM.
However we are restricting such assignments to targets that cannot be
assigned anywhere else, i.e. strictly treating them as constants.
There is no plan, at least for now, to support "initialization of registers"
in an initial statement for synthesis.
- bhasker
- J. Bhasker, Cadence Design Systems, 610-398-6312, jbhasker@cadence.com
Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
-----Original Message-----
From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of
Jim Hudson
Sent: Saturday, October 06, 2001 1:29 PM
To: VhdlCohen@aol.com
Cc: cliffc@sunburst-design.com; vlog-synth@eda.org
Subject: Re: Initial Blocks fail with Synopsys Tools
Just a note,
If your going to support the concept of being able to initialize registers
with an "initial" statement. Then the synthesis library will need to
support registers that come out of power up in a known state. It not
inconceivable to have a register that intializes to a
given state, then on a signal reset, have the opposite state. Not that I
think that this feature
would be highly desired, but remember we need to keep it such that the
behavioral
operates the same as the gate level. Power up, reset conditions have
often been the
case why large designs once in gate level come up all X, and once the X's
propogates,
its a bitch to debug. Often its a problem with the way the silicon
vendors implement
the "library" elements. Lets face it, real registers never power up in an
X state, there
is no such beast. So I suggest being careful on how you implement it!
Implement it
such that it can and should be modeled the way the real silicon operates.
And the
Silicon vendors should create their libraries to operate in this manner
also.
This is possible in CELL design to create registers that do this. But the
synthesis tool
needs to know about theses cells and needs to be able to select which cell
to implement
from the "initial" statement, and reset conditions.
-jim hudson
www.asic-crafters.com
408-554-1316
VhdlCohen@aol.com wrote:
For the record, Synplify provides WARNINGS! Below is portion of report:
$ Start of Compile
#Sat Oct 06 09:54:48 2001
Synplicity Verilog Compiler, version 6.2.0, Build 097R, built Apr 16
2001
Copyright (C) 1994-2000, Synplicity Inc. All Rights Reserved
@I::"c:\__dsgn\dff.v"
Verilog syntax check successful!
Selecting top level module dff
Synthesizing module dff
@W:"c:\__dsgn\dff.v":6:3:6:9|Ignoring initial statement
@END
In a message dated 10/5/01 6:07:38 PM Pacific Daylight Time,
cliffc@sunburst-design.com writes:
I was very surprised to learn that Synplicity ignored initial blocks.
I
consider this to be a serious flaw in the Synplicity tools.
module dff (q, d, clk, rst_n);
output q;
input d, clk, rst_n;
reg q;
initial q <= 0;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= d;
endmodule
------------------------------------------------------------------------
----
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
http://www.vhdlcohen.com/ vhdlcohen@aol.com
Author of following textbooks:
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn
0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn
0-7923-8115
------------------------------------------------------------------------
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