Subject: RE: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
From: J. Bhasker (jbhasker@cadence.com)
Date: Mon Oct 08 2001 - 12:37:37 PDT
Meeting minutes:
Attendees:
Cliff Cummings
Ben Cohen
Stephen Boyd
Jenjen Tiao
J. Bhasker
1. Stephen presented his feedback on the synthesizability of "configs and
lib map".
He had previously sent it out on the reflector. No new issues were raised
and
the comments made by Stephen would get incorporated into the next draft.
2. Jenjen presented her feedback on synthesizability of power op and system
functions
$signed and $unsigned. Her review had been posted on the reflector prior to
the
meeting. She had identified two bugs in the 1364 LRM, and she was requested
to file
these as bugs on the BTF home page.
3. We discussed the signed type which I had reviewed for its applicability
to
synthesis. I had no comment other than that it should be synthesizable.
4. We reviewed Sashi's review of draft 1.7. All comments seemed reasonable
except 5.
There is really no template requirement to infer syn set/reset - synthesis
tools
automatically do this. A note to this effect may be added to the draft.
5. We discussed Ben's proposal on ROM/RAM modeling. It was agreed that in
the case stmt modeling style of ROM, all ROM assignments have to be done
within a single case
statement and the case expression will dictate the address of the ROM. In
the
initial stmt style, it was agreed to support initial statement that contains
only constant value assignments, i.e. targets of such assignments cannot be
reassigned anywhere else.
In addition, the initial stmt shall support the readmemb/readmemh system
tasks for
loading the value of a memory. Ben to send out an updated proposal for
review before
it gets incorporated into draft 1.8.
6. Bhasker to incorporate all comments and post updated rev 1.8 by Oct 20.
7. Next meetings date: Nov 2, Dec 7.
--J. Bhasker Cadence Design Systems 7535 Windsor Drive, Suite A200, Allentown, PA 18195 (610) 398-6312, (610) 530-7985(fax), jbhasker@cadence.com
-----Original Message----- From: owner-vlog-synth@eda.org [mailto:owner-vlog-synth@eda.org]On Behalf Of J. Bhasker Sent: Monday, October 01, 2001 11:42 AM To: vlog-synth@eda.org Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
<x-flowed> The next Verilog Synthesis Interoperability Working Group phone conference is scheduled for FRIDAY, OCTOBER 5 from 12:00pm to 1:30pm EASTERN STANDARD TIME.
Call: USA Toll Free Number: 888-603-6976 USA Toll Number: +1-312-470-0062 PASSCODE: 23024 LEADER: Mr Jayaram Bhasker
Agenda:
1. To discuss the synthesizability of the new features of Verilog-2000. Following to report on their assigned items:
- StephenBoyd - CliffCummings - JenjenTiao - MuzaffarKal - JoeWetstein : attribute format
If you cannot make it to the meeting, please post your comments on the reflector prior to the meeting. I would like to close on the 2000 features soon.
2. To continue to discuss RAM and ROM modeling - BenCohen.
3. To start reviewing the latest draft D1.7 (posted on our web site).
Future telecon dates: Nov 2, Dec 7.
Regards,
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com) Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth
</x-flowed>
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