Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01

Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Oct 5, '01
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Mon Oct 01 2001 - 08:41:34 PDT

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The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, OCTOBER 5 from 12:00pm to
1:30pm EASTERN STANDARD TIME.

Call:
USA Toll Free Number: 888-603-6976
USA Toll Number: +1-312-470-0062
PASSCODE: 23024
LEADER: Mr Jayaram Bhasker

Agenda:

1. To discuss the synthesizability of the new features of Verilog-2000.
Following to report on their assigned items:

      - StephenBoyd
      - CliffCummings
      - JenjenTiao
      - MuzaffarKal
      - JoeWetstein : attribute format

      If you cannot make it to the meeting, please post your comments on
the reflector prior to the meeting. I would like to close on the
      2000 features soon.

2. To continue to discuss RAM and ROM modeling - BenCohen.

3. To start reviewing the latest draft D1.7 (posted on our web site).

Future telecon dates: Nov 2, Dec 7.

Regards,

- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
  Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
  Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth

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