Subject: Re: Synopsys support for Verilog-2001
From: J. Bhasker (jbhasker@Cadence.COM)
Date: Wed Sep 26 2001 - 11:07:50 PDT
Shalom:
Thanks for posting this release note. The good news is that we have already
considered (or
being considered) all the Verilog features that Synopsys is supporting in their
Presto release.
- bhasker
At 12:01 PM 9/23/2001 +0300, Shalom Bresticker wrote:
>
>--
>**************************************************************************
>Shalom Bresticker Shalom.Bresticker@motorola.com
>Motorola Semiconductor Israel, Ltd. Tel #: +972 9 9522268
>P.O.B. 2208, Herzlia 46120, ISRAEL Fax #: +972 9 9522890
>**************************************************************************
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>
>HDL Compiler Release
>Note<http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/pdf/hdl.pdf>
>
>
>
>----------
>This release note presents the latest information about HDL Compiler
>version 2001.08 in the following sections:
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000005179>New
> Features, Enhancements, and Changes
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000009761>Known
> Problems and Limitations
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000005622>Resolved
> STARs
>
>
>
>New Features, Enhancements, and Changes
>
>
>
>HDL Compiler (Presto Verilog) version 2001.08 is a completely redesigned
>HDL Compiler tool enabled by default in this release. Additionally, Presto
>Verilog provides faster and more predictable elaboration time, higher
>capacity, and it supports many Verilog 2000 features from the draft IEEE
>Std 1364-2000.
>
>HDL Compiler version 2001.08 provides new features, enhancements, and
>changes as described in the following sections:
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000007916>Running
> Presto Verilog
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000008734>New
> Features Include Support for Verilog 2000
> *
> <http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000008475>Other
> Changes
>
>
>
>Running Presto Verilog
>
>
>
>The new HDL Compiler tool (Presto Verilog) is enabled by default in this
>release. To run the original HDL Compiler tool, set hdlin_enable_presto to
>false.
>
>Presto Verilog uses the same read, analyze, and elaborate commands as the
>original HDL Compiler tool, and there is no need to change any code or
>scripts. Presto Verilog is a direct replacement for the original HDL
>Compiler. It supports dcsh, Tcl, dc_shell, psyn_shell, design_analyzer,
>and design_vision.
>
>You can read in RTL files using read or analyze/elaborate commands.
>However, for parameterized designs, it is best to use analyze/elaborate
>because this method supports elaboration of parameterized subdesigns while
>read unconditionally elaborates all designs with the default parameters.
>
>Although you can read in netlists using either
>read_file -format verilog -netlist or
>read -format verilog or
>analyze -format verilog and elaborate read_file -format verilog -netlist
>for gate-level netlists because this method is faster and uses less memory.
>
>
>New Features Include Support for Verilog 2000
>
>
>
>New Presto Verilog features are listed in
><http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000008745>Table
><$chapnum>-1. Presto Verilog supports many Verilog 2000 features from the
>draft IEEE Std 1364-2000. For new feature details, see the HDL Compiler
>(Presto Verilog) Reference Manual. Table <$chapnum>-1 New Presto Verilog
>Features
>Feature Description
>
>Casting operators Allows sign control; preserves the value of the argument.
>Casting operators are $signed(), $unsigned().
>Parameter passing by name Allows setting parameters on subdesigns by
>parameter name; it is not sensitive to number or declaration order of
>parameters. You only need to specify the subset of parameters you want to set.
>Implicit event expression list Makes always blocks sensitive to any
>variable read.
>Syntax: (@*)
>The event expression does not need to list net and variable identifiers;
>they are automatically added to the event expression. If you do not use
>this syntax and the tool finds an incomplete sensitivity list, the tool
>will issue a warning.
>ANSI-C-style port declaration You can list types when declaring port
>values. For example,
>module test (input [3:0] D, input clk, input reset, output [3:0] Q);
>Array of instances This feature enables instantiations of modules that
>contain a range specification.
>Signed/unsigned constants, parameters, nets, and registers Example of
>signed nets module adder ( input [2:0] a, input [2:0] b, output [3:0] z];
>wire signed [2:0] x = a; wire signed [2:0] y = b; assign z = x - y // This
>will result in a signed adder endmodule
>New array functionality Multidimensional arrays
>Arrays of nets Presto Verilog supports multidimensional arrays of any
>variable or net data type. Example: reg [3:0] Z [0:3] [0:7] [0:3];
>New operators Indexed part select addressing ([+:] and [-:] operators) -
>Presto Verilog supports the variable part-select introduced by Verilog
>2000. This enables the user to select a group of bits from a vector using
>a variable base address.
>Power operator (**)
>Arithmetic shift operators (<<< and >>>) -These operators allow the user
>to shift an expression to the right or to left and still maintain the sign
>of the value.
>New compiler directives
>`ifndef, `elsif, `undef Presto Verilog supports `ifndef, `elsif, `undef.
>Comma-separated sensitivity lists Signals in the sensitivity list can be
>separated with commas.
>Displays synthesis progress Reports on synthesis progress. This is helpful
>for printing out compile-time computations on parameters or the number of
>times a loop executes.
>Uses the system task - $display.
>Models simulator behavior Simulates simulator behavior by allowing writing
>to out-of-bounds array locations using the new variable
>hdlin_dyn_array_bounds_check.
>Expanded MUX-OP inference Get MUX-OPs for both case and if statements and
>right-hand side variable array reference x[a].
>Resource sharing directives Support for manual resource sharing
>implementation selection and the following directives: label,
>map_to_module, add_ops, may_merge_with, don't_merge_with, label_applies_to.
>
>
>Other Changes
>
>
>
>The following changes were made in HDL Compiler version 2001.08.
>
>
>Documentation Changes
>
>
>
>For Presto Verilog, the content of the Guide to Coding Styles for
>Synthesis version 2001.08 document is incorporated into the HDL Compiler
>(Presto Verilog) Reference Manual.
>
>
>Cannot Specify Architectures in Modules
>
>
>
>The original Verilog HDL Compiler tool allows you to specify architectures
>for modules, which is not in accordance with IEEE Std 1364. In Presto
>Verilog, this nonstandard behavior is not available. Module names of the form
>e__a ("e" and "a" separated by two underscores) are not interpreted as of
>, but rather as
>, as illustrated in this example:
>
> module e__a(...);
> ...
> endmodule
>
>After analyzing the code in the example, you cannot elaborate it as
>
> dc_shell> elaborate e -arch a
>
>It was possible to do so with the original HDL Compiler tool. The new
>functionality in Presto Verilog is consistent with standard Verilog. To
>run the original HDL Compiler, set hdlin_enable_presto to false.
>
>
>Known Problems and Limitations
>
>
>
>This section describes known problems, limitations, and possible
>workarounds in HDL Compiler version 2001.08.
>
>
>Implicit State Machine Not Supported
>
>
>
>HDL Compiler (Presto Verilog) version 2001.08 does not support implicit
>state machines--using multiple @(posedge clk) constructs within an always
>block (multiple wait statements are not supported). To create a sttate
>machine, you need to use the coding style described in the HDL Compiler
>(Presto Verilog) Reference Manual.
>
>
>Documentation Correction
>
>
>
>The VHDL Compiler Reference Manual, page 10-4, recommends synthesis_off/on
>rather than translate_off/on. This is incorrect--using synthesis_off/on
>can lead to extra logic. (Star#111780). Instead, use translate_off/on with
>hdlin_translate_off_skip_ttext set to true. Also, do not use
>translate_off/on for designs where analyzed results can be used with VSS.
>
>
>Resolved STARs
>
>
>
>The Synopsys Technical Action Requests (STARs) listed in
><http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000010242>Table
>1 are resolved in Presto Verilog version 2001.08. Table 1 Resolved Presto
>Verilog STARs
>STAR ID Title
>125811 Tool fatals when translate_off and translate_on are not used.
>125417 Bad Logic after read of shift operation in 2000.11-sp1 (presto
>enabled)
>125190 Presto bad logic bug. When parameters greater than 32 bits are
>passed to sub-designs, they are either given a wrong value, or the tool
>fatals.
>124785 Verilog Presto Fatals when DC-tcl is used, but passes with dc_shell
>script.
>124732 Presto fatals when a verilog netlist is read using read_verilog.
>124278 Presto fatals during elaboration phase.
>124101 Presto fatals when dynamic array bounds checking is turned on.
>123908 Presto crashes with "not enough memory" message, when Verilog RTL
>is read in.
>123293 Presto fatals during elaboration phase.
>122359 Presto does not generate an error when two terminals have exactly
>same names in an instance.
>122280 Presto fatals during ` verilog_read' command
>121921 Presto returns error, if a signal is declared as: input [0:0] in1;
>instead of: input in1;
>121639 Presto incorrectly interprets synchronous set and reset signals
>121023 When the defparam statement is used, the output netlist contains
>unmapped logic in the sub-block.
>120489 Presto fatals when non-blocking assignment statements are used for
>multi-dimension arrays.
>120431 Presto generates incorrect logic when there is a case statement
>inside a function, and the function is called from different processes.
>120278 Presto generates illegal logic, e.g. nets with multiple drivers,
>which produces errors during compilation.
>120224 Presto creates multiple drivers when the same variable, e.g. 'i',
>is used as the loop index in multiple blocks. For 2001.08 release, presto
>will not create illegal design and will generate error in this situation.
>120027 Presto produces VER-37 internal error when reading in Verilog code.
>119868 Presto fatals with the following code: .... In 2001.08 release,
>Presto will issue a warning that an aggregated port has mixed directions
>in it's components.
>119843 Presto hangs while reading in a big Verilog file.
>119618 Presto takes longer to read in same Verilog code, as compared to
>the old HDL Compiler.
>119119 Presto reads in standard.sldb twice, due to which the set_dont_use
>command cannot identify standard.sldb as a unique library.
>118349 Presto produces a fatal error when parameters are used in wire
>declaration. The fatal error goes away when the parameter (in a signed
>wire declaration) is substituted with its actual value.
>118345 Presto generates 32x32 multiplier for Verilog code of 16x16
>multiplier.
>118227 Presto 2000.11 hangs with commands read_file, analyze/elaborate or
>read_verilog, but Presto 2000.05 goes through.
>117843 Presto produces incorrect GTECH mapping.
>117764 Presto fatals during elaboration with a design that contains
>parameters.
>117599 Presto incorrectly reads defparam statement.
>116763 Presto fatals when reading a Verilog netlist using 'read_verilog'
>command.
>115963 Presto 2000.11 terminates with VER-37 internal error with read
>command, but passes with Presto 2000.05.
>113486 Presto produces incorrect logic when a wire is connected to logic
>0, as well as to the output of a gate. For 2001.08 release, presto will
>not create incorrect logic and will generate ELAB-368 error in this situation.
>105892 Presto crashes when the input Verilog code has syntax errors.
>
>The Verilog Synopsys Technical Action Requests (STARs) listed in
><http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000010403>Table
>2 are resolved in the original HDL Compiler version 2001.08. Table 2
>Resolved Original Verilog HDL Compiler STARs
>STAR ID Title
>124332 Man page VER-91 has incorrect information. This problem has been
>fixed in the 2001.08 release. The VER-91 message is replaced by the more
>appropriate ELAB-338 message.
>124133 HDL Compiler generates incorrect logic for Verilog designs that
>contain the following constructions: - A Verilog parameter declaration
>with no declared type, whose definition is supplied by a right-shift
>expression (>>) - A part-select or subscript operation on that Verilog
>parameter
>120899 Bad logic is generated if a parameter is overwritten at the parent
>level in the child instantiation, and if any of the following conditions
>are met: 1) If either dc_shell or dc_shell-t are evoked with the -no_init
>switch. 2) If the analyze and elaborate steps are executed from within a
>tcl procedure.
>119984 When two busses are concatenated the output verilog netlist does
>not retain the original bus structure.
>119909 Fatal error when simple variables are not used in the event
>expression with 'posedge' or 'negedge' qualifier.
>119025 Both Presto and HDL Compiler produce fatal error during
>elaboration. This problem has been corrected in 2001.08 version of Presto
>only, as Presto is the default compiler in the 2001.08 release.
>116428 HDL Compiler crashes when a very large verilog netlist is read in
>using 'read_verilog' command.
>106884 When 'hlo_resource_allocation' is set to 'constraint_driven', it
>provides smaller area than when set to 'area_only'.
>
>The VHDL Synopsys Technical Action Requests (STARs) listed in
><http://solvnet.synopsys.com/cgiservlet/aban/cgi-bin/ASP/get_html/html/SynopsysDocumentation/2001.08/hdl.htm#1000010075>Table
>3 are resolved in the HDL Compiler version 2001.08. Table 3 Resolved VHDL
>STARs
>STAR ID Title
>115821 Design Compiler crashes with input VHDL files, but goes through
>when the order or analysis is changed.
>58986 When timing constraints are not set, the following code produces two
>adders: z <= a + b + c; where c is one-bit integer. In 2001.08 release,
>HDL compiler is enhanced to produce one adder with a carry-in bit, even
>when timing constraints are not set.
>
>
>----------
>E-mail your comments about Synopsys documentation to
><mailto:docs@synopsys.com>docs@synopsys.com
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J. Bhasker
Cadence Design Systems
7535 Windsor Drive, Suite A200, Allentown, PA 18195
610.398.6312, 610.530.7985 (fax), jbhasker@cadence.com
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