Subject: Re: Verilog Synthesis draft 2.0 // Comments // Krishna RSVP
From: VhdlCohen@aol.com
Date: Mon Feb 25 2002 - 10:31:28 PST
> <4. Verification Methodology
> ..."This also implies that the port list of the synthesized result must be
> the
> same as the original model - ports cannot be added or deleted during
> synthesis."
> We discussed "probe" on wire or reg, to preserves internal nets for probing
> causing them to appear as ports at the top level. The "probe" pragma is
> not on the list, and that one DOES add PORTS on the netlist.
> [J. Bhasker] From my notes, it appears that we did not close on this topic,
> as we could not define what was meant by "top level". Let me know if this
> is not consistent with what we had decided in the meeting>
[BEN] Let's rewrite the "probe" as:
probe :
This attribute preserves internal net for probing causing them to appear as
ports on the top level of the hierarchy being synthesized.
// comment to panel. This attribute is needed for the verification of
gate-level model designs ot the "grey-box" level where internal signals may
be needed for triggering of events in verifier (example, the occurrence of a
simulatation push/pop of a fifo. It is also needed for hardweare debugging
when a difficult bug occurs.
> 5.3 Modeling level-sensitive storage devices
> No mention is made for the following:
> always @ (ENABLE or D)
> if (ENABLE)
> Q = D;
> else Q = Q;
> // Looks like a non-latch, but is a latch
>
> [J. Bhasker] According to the rules listed, Q is not a latch.
>
[BEN] I disagree with your above comment. Q IS a latch in HDL, including
VHDL, because the without the "else" the "Q <= Q" is implicit, since Q must
hold its value if conditionfails. Below is an example synthesized with
Synplicity's Synplify Pro, and their tools thinks it's a latch. Perhaps this
needs more discussions.
module latch (q, d, ldenb);
parameter WIDTH = 1;
output [WIDTH-1:0] q; // output
input [WIDTH-1:0] d; // data input
input ldenb; // load enable
reg [WIDTH-1:0] q; // FF output
always @(ldenb or d)
if (ldenb) q <= d;
else q <= q; // Line 10
endmodule //latch
Synplicity Verilog Compiler, version 7.0.0, Build 130R, built Nov 16 2001
@I::"C:\__DSGN\latch.v"
Verilog syntax check successful!
File C:\__DSGN\latch.v changed - recompiling
Selecting top level module latch
Synthesizing module latch
@N:"C:\__DSGN\latch.v":10:11:10:11|Removing redundant assignment
@W:"C:\__DSGN\latch.v":9:1:9:2|Latch generated from always block for signal
q[0], probably caused by a missing assignment in an if or case stmt
@END
> 6.1.4 Miscellaneous Attributes
> synthesis, keep
> The following sentence is anbiguous and not clear. What does " no
> optimizations to occur across the specified reg boundaries" mean?
> "The presence of the attribute shall cause no optimizations to occur across
> the speci.ed reg (which has been
> inferred as an edge-sensitive storage device) boundaries. This attribute
> does not apply if the reg has not been
> inferred as an edge-sensitive storage device."
> [J. Bhasker] Can you suggest a better wording?
My problem is with the meaning of "The presence of the attribute shall cause
no optimizations to occur across the specified reg (which has been
inferred as an edge-sensitive storage device) boundaries". What does
optimizations across a sepcified register or sequential element mean?
Does that mean that if I have a binary counter, it cannot be modified to a
one-hot?
Does it mean that if I don't use the MSB of that counter (or reg), it has to
be kept?
Does it mean that if I have unused combinational logic that isa connect to
the reg, it has to be kept?
I need clarification from this audiance. I also would like some
calrification in the document. <A HREF=" ">Krishna, perhaps you could explain. Thanks. </A>
Ben
---------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
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* Component Design by Example ", 2001 isbn 0-9705394-0-1
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* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
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