Subject: Re: Verilog Synthesis draft 2.0 // Comments // Krishna RSVP
From: Krishna Garlapati (krishna@synplicity.com)
Date: Mon Feb 25 2002 - 11:42:34 PST
VhdlCohen@aol.com wrote:
>
> My problem is with the meaning of "The presence of the attribute shall
> cause no optimizations to occur across the specified reg (which has been
> inferred as an edge-sensitive storage device) boundaries". What does
> optimizations across a sepcified register or sequential element mean?
One way to look at it is, the reg or flop acts like a reference point
and also prohibits any
information flow upstream. This implies, all loads of the flop just see
the flop and only the
flop.
As a side effect the attribute also disables extraction of higher level
objects or abstraction.
>
> Does that mean that if I have a binary counter, it cannot be modified
> to a one-hot?
yes.
>
> Does it mean that if I don't use the MSB of that counter (or reg), it
> has to be kept?
yes.
>
> Does it mean that if I have unused combinational logic that isa
> connect to the reg, it has to be kept?
no.
-- - Krishna. Synplicity Inc. (408)215-6152
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