Subject: Re: (* synthesis, keep [=
One of goals of the KEEP is to prevent optimization of a design when all the
2. Keep ALL in an upwward direction?
Issues to discuss.
This archive was generated by hypermail 2b28
: Fri Feb 08 2002 - 08:52:00 PST
From: VhdlCohen@aol.com
Date: Fri Feb 08 2002 - 08:46:52 PST
pieces are not there. This is useful when it is necessary to evaluate the
performance of a partial design, without having the synthesis tool blow away
most of the design.
Issues in the keep are:
1. Keep ALL in a downward direction?
-- If keep is at the module declaration level, like:
module xyz (a, b,c)(* synthesis syn_keep= all *);
module xyz (a, b,c)(* synthesis syn_keep= downward*); //?
then everything within the module is kept, and no optimization within the
design is performed.
I guess, that would include instances within the design.
instanceX instanceX(...)(* synthesis syn_keep= all *);
instanceX instanceX(...)(* synthesis syn_keep= upward*);
Optimation of instanceX is allowed ?? but all the drivers and everything
upward that has anything to do with pins of that instance are kept??
Do we want this?
----------------------------------------------------------------------------
Ben Cohen Publisher, Trainer, Consultant (310) 721-4830
<A HREF="http://www.vhdlcohen.com/">http://www.vhdlcohen.com/> vhdlcohen@aol.com
Author of following textbooks:
* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn
0-9705394-2-8
* Component Design by Example ", 2001 isbn 0-9705394-0-1
* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1
* VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115
------------------------------------------------------------------------------