1. RHS is used in the text, but is not in the definitions list.
Something like the following might be used:
RHS Right-hand side. Value or expression to be assigned to
destination argument.
2. On page 9, the c) comment is not clear. Perhaps something like:
Clock and/or input data transitions must be delayed until
after asynchronous set/reset signals have been released. The delay must be
long enough to avoid a clock and/or data setup/hold time violation.
3. I think we may add confusion unless we change the instances of !
<condB> to ~<condB>. As you know, these are equivalent only if condB is a
single bit variable. All uses of ! should be looked at (like the use of
!CLEAR).
4. It would probably aid readability of the examples if all the Verilog
keywords were bold (always, if, else, etc.).