Subject: Re: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Jan 11, '02
From: Paul Graham (pgraham@cadence.com)
Date: Fri Jan 11 2002 - 12:44:17 PST
> In my verilog code I have the following attributes which I think we need to
> add to ambit list:
>
> parameter [3:0] // ambit synthesis enum txenstate ...
> // ambit synthesis state_vector txenstate -encoding one_hot
> reg [3:0] /* ambit synthesis enum txenstate */ txenstate_d, txenstate;
I believe these are basically equivalent to Synopsys pragmas. Ambit also
supports the case={full,parallel} pragma, but since I know there's a Synopsys
equivalent I didn't include it on my list. I only listed those pragmas
for which I didn't know of a Synopsys equivalent.
Paul
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