Subject: Re: verilog 2000 feature list
From: VhdlCohen@aol.com
Date: Wed Sep 27 2000 - 09:50:04 PDT
In a message dated 9/27/00 9:00:07 AM Pacific Daylight Time,
jbhasker@Cadence.COM writes:
> >> Are you sure that re-entrant tasks and functions can be
> >> synthesized? Obviously reentrant tasks that have no recursion can
> >> easily be synthesised; and presumably with analysis, limited tail
> >> recursion could be figured out, but the general case may prove too
> >> challenging.
> --Good point. We have two choices here:
> -- A. not to support recursive calls
> -- B. to allow recursion where the number of recursions is bounded by a
> -- static value
>
In Synopsys's coding guidelines "User HDL Coding Styles: Synthesis
Application Note"
file synco_3.pdf page 19 (in Synopsys user CD), the following example of a
recursive function in VHDL is provided. I like suggestion B.
function XOR_tree_func(data: std_logic_vector) return std_logic is
variable UPPER_TREE, LOWER_TREE: std_logic;
variable MID, LEN: natural;
variable result: std_logic;
variable i_data: std_logic_vector(data’LENGTH-1 downto 0);
begin
i_data := data;
LEN := i_data’LENGTH;
if LEN = 1 then
result := i_data(i_data’LEFT);
elsif LEN = 2 then
result := i_data(i_data’LEFT) XOR i_data(i_data’RIGHT);
else
MID := (LEN + 1)/2 + i_data’RIGHT;
UPPER_TREE := XOR_tree_func(i_data(i_data’LEFT downto MID));
LOWER_TREE := XOR_tree_func(i_data(MID-1 downto i_data’RIGHT));
result := UPPER_TREE XOR LOWER_TREE;
end if;
return result;
end;
--------
The complete application example is shown below:
The VHDL version shown in Example 3-11 uses recursion to build a
tree.
Example 3-11 VHDL for XOR Tree
library IEEE;
use IEEE.std_logic_1164.all;
entity XOR_tree is
generic (N: natural := 4);
port (data_in: in std_logic_vector(N downto 0);
data_out: out std_logic);
end XOR_tree;
architecture one of XOR_tree is
function XOR_tree_func(data: std_logic_vector) return std_logic is
variable UPPER_TREE, LOWER_TREE: std_logic;
variable MID, LEN: natural;
variable result: std_logic;
variable i_data: std_logic_vector(data’LENGTH-1 downto 0);
begin
i_data := data;
LEN := i_data’LENGTH;
if LEN = 1 then
result := i_data(i_data’LEFT);
elsif LEN = 2 then
result := i_data(i_data’LEFT) XOR i_data(i_data’RIGHT);
else
MID := (LEN + 1)/2 + i_data’RIGHT;
UPPER_TREE := XOR_tree_func(i_data(i_data’LEFT downto MID));
LOWER_TREE := XOR_tree_func(i_data(MID-1 downto i_data’RIGHT));
result := UPPER_TREE XOR LOWER_TREE;
end if;
return result;
end;
begin
data_out <= XOR_tree_func(data_in);
end one;
------------------------------------------------------
VhdlCohen Training, Consulting, Verification
Ben Cohen vhdlcohen@aol.com (310) 721-4830
http://www.vhdlcohen.com/
Author of following textbooks:
VHDL Coding Styles and Methodologies, 2nd Edition,
isbn 0-7923-8474-1 Kluwer Academic Publishers, 1999
VHDL Answers to Frequently Asked Questions, 2nd Edition,
isbn 0-7923-8115-7 Kluwer Academic Publishers, 1998
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