Subject: RE: verilog 2000 feature list
From: Jayaram Bhasker (jbhasker@Cadence.COM)
Date: Wed Sep 27 2000 - 08:51:09 PDT
Mac:
>> Are you sure that re-entrant tasks and functions can be
>> synthesized? Obviously reentrant tasks that have no recursiob can
>> easily be synthesised; and presumably with analysis, limited tail
>> recursion could be figured out, but the general case may prove too
>> challenging.
Good point. We have two choices here:
A. not to support recursive calls
B. to allow recursion where the number of recursions is bounded by a
static value
- bhasker
> From mac@verisity.com Wed Sep 27 10:51 EDT 2000
> From: Michael McNamara <mac@verisity.com>
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> Date: Wed, 27 Sep 2000 07:51:16 -0700 (PDT)
> To: Jayaram Bhasker <jbhasker>
> Cc: vlog-synth@eda.org
> Subject: RE: verilog 2000 feature list
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>
> Jayaram Bhasker writes:
> > ----------
> > X-Sun-Data-Type: text
> > X-Sun-Data-Description: text
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> > X-Sun-Content-Lines: 4
> >
> > Attached is a verilog-2000 feature list and
> > my initial feedback on its applicability for synthesis.
> >
> > - bhasker
> > ----------
> > X-Sun-Data-Type: default
> > X-Sun-Data-Description: default
> > X-Sun-Data-Name: vlog2000.txt
> > X-Sun-Charset: us-ascii
> > X-Sun-Content-Lines: 78
> >
> > This document lists the new Verilog 2000 features and
> > suggests to its synthesizability:
>
> I agree with most of your suggestions; however for item 5 I have a
> comment (included)
>
> >
> >
> > FEATURE SYNTHESIZABLE?
> > ------- --------------
> >
> > 1. Generate block (for, ifelse, case) Yes
> >
> > 2. Multidimensional arrays Yes
> >
> > 3. Bit and part-select with arrays Yes
> >
> > 4. Enhanced file I/O No
> >
> > 5. Re-entrant tasks and functions Yes
>
> Are you sure that re-entrant tasks and functions can be
> synthesized? Obviously reentrant tasks that have no recursiob can
> easily be synthesised; and presumably with analysis, limited tail
> recursion could be figured out, but the general case may prove too
> challenging.
>
> >
> > 6. Configuration block Yes
> >
> > 7. Library map files Yes
> >
> > 8. Named parameter association Yes
> >
> > 9. Comma sep sensitivity list Yes
> >
> > 10. Event symbol @* Yes
> >
> > 11. ANSI style I/O decls Yes
> >
> > 12. Automatic width extension beyond 32 bits Yes
> >
> > 13. Indexed part select Yes
> >
> > 14. Reg initial declaration No
> >
> > 15. Signed type Yes
> >
> > 16. System functions $signed, $unsigned Yes
> >
> > 17. Constant functions Yes
> >
> > 18. Addtl cond compilation(`ifndef,`elsif,`undef) Yes
> >
> > 19. Power op (**) Yes - first operand is 2, or
> > opds are constants.
> >
> > 20. 'line compiler directive Yes (ignored)
> >
> > 21. Arithmetic shift ops (<<<, >>>) Yes
> >
> > 22. Combined port and data type decl Yes
> >
> > 23. Parallel case attribute Yes
> > (* rtl_synthesis_parallel_case *)
> >
> > 24. Full case attribute Yes
> > (* rtl_synthesis_full_case *)
> >
> > 25. Conditional compilation attribute Yes
> > (* rtl_synthesis_on *) (* rtl_synthesis_off *)
> >
> > 26. On-detect pulse error propogation No
> > (pulsestyle_onevent, pulsestyle_ondetect)
> >
> > 27. Negative pulse detection No
> > (showcancelled, noshowcancelled)
> >
> > 28. New timing checks No
> > ($removal, $recrem, $timeskew, $fullskew)
> >
> > 29. Negative timing constraint No
> > (modified $setuphold)
> >
> > 30. New VCD system tasks No
> >
> > ------------------------
> >
> > - J. Bhasker, September 26, 2000
> >
>
> --
> //' Michael McNamara <mac@verisity.com>
> _ // Sr VP Technology 650-934-6888
> \ // Verisity Design 650-934-6801 FAX
> \// <http://www.verisity.com> 408-202-1137 Cell
> --------------------------------------------------------------
> Get my verilog emacs mode from <http://www.verilog.com>
>
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