Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01

Subject: Verilog Synthesis Interoperability Working Group Meeting: Agenda for Aug 10, '01
From: Jayaram Bhasker (jbhasker@cadence.com)
Date: Mon Aug 06 2001 - 08:49:31 PDT

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The next Verilog Synthesis Interoperability Working Group phone
conference is scheduled for FRIDAY, AUGUST 10 from 12:00pm to 1:30pm
EASTERN STANDARD TIME.
   
Call:
  USA Toll Free Number: 888-391-6578
  USA Toll Number: +1-712-257-3711
  PASSCODE: 31982
   
Agenda:
   
1. To discuss the synthesizability of the new features
   of Verilog-2000. Following to report on their assigned items:
   
     - StephenBoyd
     - SashiObilisetty
     - CliffCummings
     - KenCoffman
     - GilbertNguyen
     - JenjenTiao
     - MuzaffarKal
     - JoeWetstein : attribute format
     
     It would be nice if you can send your feedback prior to the meeting
     so everyone has a chance to review it.

2. To continue to discuss RAM and ROM modeling - BenCohen.
   
Future telecon dates: Sept 7 (PLEASE NOTE CHANGE!), Oct 5.

Regards,
   
- J. Bhasker, Cadence Design Systems (610-398-6312, jbhasker@cadence.com)
 Chair, IEEE 1364.1 Verilog Synthesis Interoperability Working Group
 Email: vlog-synth@eda.org, URL: http://www.eda.org/vlog-synth

• Next message: VhdlCohen@aol.com: "Re: Assigning / testing different sizes -- shouldn't we restrict the use?"
• Previous message: Michael McNamara: "Re: constant function"
• Messages sorted by: [ date ] [ thread ] [ subject ] [ author ]

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